circuit reliability


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circuit reliability

[′sər·kət ri‚lī·ə′bil·əd·ē]
(communications)
The percent of time a circuit was available to the user during a specified period of time.
References in periodicals archive ?
For a combinational logic circuit with [N.sub.in] primary inputs, [N.sub.out] primary outputs, and [N.sub.g] logic gates, the problem of evaluating the signal reliability of all primary outputs and their joint reliability (i.e., the overall circuit reliability [R.sub.C]) can be solved by exhaustively calculating all [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] scenarios.
The circuit reliability (i.e., the probability of outputs being correct) is evaluated by comparing its PTM and ITM.
For instance, in [10], the observability of a gate g is defined as the ratio of the error probability of the whole circuit and the error probability [[epsilon].sub.i] of this gate, that is, (1 - [R.sub.C]([[epsilon].sub.i]))/[epsilon], where [R.sub.C]([[epsilon].sub.i]) is the circuit reliability when the only unreliable gate is ith gate (with all other gates being error-free).
The circuit reliability is found to be [R.sub.C] = 0.8658 with the runtime of 0.2798 s.
where [R.sub.C] is again the circuit reliability. Since the circuit reliability usually decreases with the circuit size ([N.sub.g]), the [N.sub.MC] will increase with the circuit size for a given accuracy (measured by CV).
One of the main features with PGM is that the circuit reliability is analyzed by exhaustively evaluating each input combination and output.
The value of this observability can be simply defined as [o.sub.i] = (1 - [R.sub.C]([[epsilon].sub.i] = 1)), where [R.sub.C]([[epsilon].sub.i] = 1) is the circuit reliability given a single error with the current gate, and can be calculated using Boolean differences [29], symbolic techniques (such as BDDs), or simulation method.
For a single-fault case (i.e., only one gate in the circuit is erroneous), the circuit reliability (assuming a single primary output) can be simply calculated by considering each fault case individually.
Based on these assumptions, a closed-form expression for the circuit reliability of the circuit (assuming a single primary output) can be written generally as a function of error probabilities and observabilities of all gates [26]; that is,
How a flex circuit is formed and handled during assembly can have a major impact on circuit reliability. For better or worse, most flex circuit forming is done by the end-user.
The Calibre PERC platform provides circuit reliability checking technology that goes beyond the scope of traditional DRC and ERC tools, so designers and foundries can implement highly complex checks that are customized to specific design styles and foundry manufacturing processes.