clocked flip-flop

clocked flip-flop

[′kläkt ′flip‚fläp]
(electronics)
A flip-flop circuit that is set and reset at specific times by adding clock pulses to the input so that the circuit is triggered only if both trigger and clock pulses are present simultaneously.
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References in periodicals archive ?
The D Flip Flop is by far the most important of the clocked flip-flops as it never assures that inputs S and R are equal to one at the same time.