Each CLB module can not only be used to implement combinational logic
and sequential logic, but also can be configured for distributed RAM and distributed ROM.
Model of FPGA will be finalized once the synthesis is complete and the number of combinational logic
blocks and lookup tables used to implement the design.
One example is the codification presented by  where the combinational logic
circuits can be represented by a sum of products of the system logic variables (Fig.
Mohanram, "Gate sizing to radiation harden combinational logic
," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.
(i) CEN: combinational logic
, encoded select lines, and noninverting logic,
As it is known, the full adder is a combinational logic
circuit performing addition of three binary digits.
 Wojciechowski, W.S., Multiple-Valued Combinational Logic
Design Using Theorem Proving, Ph.D.
Also available is a free CLC Configuration Tool, to streamline the setup process of the CLC module by simulating the functionality of the registers and combinational logic
in a graphical user interface (GUI).
FPGA packages, as a general feature, have maximum size Combinational Logic
Blocks (CLBs) constraints much larger than the number of input-output pins IOBs.
They cover digital logic gates, Boolean algebra and logic gates, combinational logic
gates, number systems, conversions, codes, binary addition and subtraction, digital timing and signals, sequential logic gates, counters and shift registers, data conversion, and advanced digital concepts.
Scan technology was developed as a structured test technique that divided the complex sequential nature of a design into small combinational logic
blocks that could be tested individually.