cyclic redundancy check


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cyclic redundancy check

[′sīk·lik ri′dən·dən·sē ‚chek]
(computer science)
A block check character in which each bit is calculated by adding the first bit of a specified byte to the second bit of the next byte, and so forth, spiraling through the block.

cyclic redundancy check

(algorithm)
(CRC or "cyclic redundancy code") A number derived from, and stored or transmitted with, a block of data in order to detect corruption. By recalculating the CRC and comparing it to the value originally transmitted, the receiver can detect some types of transmission errors.

A CRC is more complicated than a checksum. It is calculated using division either using shifts and exclusive ORs or table lookup (modulo 256 or 65536).

The CRC is "redundant" in that it adds no information. A single corrupted bit in the data will result in a one bit change in the calculated CRC but multiple corrupted bits may cancel each other out.

CRCs treat blocks of input bits as coefficient-sets for polynomials. E.g., binary 10100000 implies the polynomial: 1*x^7 + 0*x^6 + 1*x^5 + 0*x^4 + 0*x^3 + 0*x^2 + 0*x^1 + 0*x^0. This is the "message polynomial". A second polynomial, with constant coefficients, is called the "generator polynomial". This is divided into the message polynomial, giving a quotient and remainder. The coefficients of the remainder form the bits of the final CRC. So, an order-33 generator polynomial is necessary to generate a 32-bit CRC. The exact bit-set used for the generator polynomial will naturally affect the CRC that is computed.

Most CRC implementations seem to operate 8 bits at a time by building a table of 256 entries, representing all 256 possible 8-bit byte combinations, and determining the effect that each byte will have. CRCs are then computed using an input byte to select a 16- or 32-bit value from the table. This value is then used to update the CRC.

Ethernet packets have a 32-bit CRC. Many disk formats include a CRC at some level.
References in periodicals archive ?
Ultra3 SCSI has six new features in its specification, including Double Transition Clocking (DTC), Cyclic Redundancy Check (CRC), Domain Validation, Protection for Asynchronous Information Phase (AIP), Packetization, and Quick Arbitration and Selection (QAS).
Other on-chip functions include a Cyclic Redundancy Check (CRC) generator, a PLL and flexible clock tree to support all on-chip clocks, support for direct drive of a color TFT-LCD panel up to WQVGA resolution, and an on-chip debug capability through a JTAG interface with a high-speed tracing option.
Support for advanced physical layer features including data whitening, forward error correction (FEC), and cyclic redundancy check (CRC) support, all of which are designed to enhance end-to-end system performance
In addition, with packetized SCSI, Cyclic Redundancy Check (CRC) is automatic, protecting all transmissions.

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