With ADN465x devices, high-speed serial LVDS signals can now be directly isolated without needing to deserialize
as compared to previous custom implementations.
The Windows communication foundation (WCF) framework can serialize and deserialize
these two types of data formats.
To receive an agent destination host needs to authenticate client, decode the agent, deserialize
the agent class and state, instantiate the agent, restore the agent state and resume agent execution.
The circuits used in JBODs and hubs differ substantially from SerDes since, for the most part, these systems do not deserialize
data, but rather route serial data within the system.
Although KELI has to deserialize
item content and check for consistency when chasing links, link chasing latency is just slightly slower to that of pure RDMA Read reported in Figure 3.
In displays, for example, SerDes may be used to serialize the parallel data, transmit the data across a medium using a high speed differential technology, and then deserialize
the data back to its original parallel form for the display to use.
The Tektronix TMS817 and TMS818 PCI Express Bus Support products include the hardware preprocessing necessary to deserialize
, descramble, and decode PCI Express signals before they can be input to a logic analyzer.
It allows abstracting away the need to serialize and deserialize
request and response messages manually.
Part of the High Speed Logic family of devices, the 1385DX, with its high sensitivity latched comparator input and auto-synchronizing demultiplexer, enables test and measurement, defense, and aerospace designers to develop high speed data acquisition front ends and to deserialize
high speed signals.
The server stub deserializes
the parameters from the raw message (4), and then calls the server function (5) passing it the arguments that it received from the client using the standard calling sequence.
The multiplexers located at the input stage of the FPGA logic deserializes
the input data to 64 bits in most cases (e.g., 10 G Ethernet  and GTH transceivers ).
The device's two receivers include a clock and data recovery circuit (CDR) that automatically detects the incoming serial data rate, extracts the clock and deserializes
the data into a 5-bit LVDS stream.