die shrink

die shrink

Reducing the size of the elements on a chip without changing its fundamental circuit design. In a die shrink, the internal design of the transistor may or may not be the same. For example, when the Intel Sandy Bridge microarchitecture was superseded by Ivy Bridge, the circuit design remained the same, but the transistors were entirely different. See half node and microarchitecture.
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While this process resulted in a die shrink at this early stage it's typical to have a lower yield rate, which has been built into the estimate of $99 versus the previous device cost of $76.
Intel offers a true die shrink with its second-generation 14 nm Tri-Gate process, relative to alternative FinFET technologies.
The changes this time around are far less sweeping, with the processing die shrink from 32nm to 22nm being the biggest news.
It's functionally the same ASIC [as the Bloom I] but we've done a die shrink," said Brocade's marketing vice president Jay Kidd.
With typical package footprints at 10 to 30 percent of the SOIC packages, a total die shrink for all internal components was in order.
Die shrink has led to cost reductions; TriQuint pioneered in this area," said Balut.
The company will need to hit 64 or 96-layers to hit its intended cost targets, and it might need a die shrink as well.
That degree of power savings does imply that Sony did a die shrink for the PS4, but whether they built it on 20nm or 14nm is open to speculation for now.
Beyond a die shrink and a new case design, we mentioned 802.
The 14nm die shrink for Jaguar seems more likely, but until Sony confirms the details we won't know for certain.
According to Theo Valich, Sony initially planned on doing a straight die shrink from 28nm to 14nm, but didn't want to pay the cost of moving from a 28nm planar design to a 14nm FinFET architecture.
Historically, TSMC has led the pure-play foundry business in deploying new manufacturing technologies, and therefore won the overwhelming majority of business for each die shrink.