The current [i.sub.2] generates a voltage drop on resistance [R.sub.2], which provides the differential output voltage
Total differential output voltage
accuracy is [+ or -]1 percent over the -40[degrees]C to 125[degrees]C operating junction temperature range.
where [v,sub.1d], [v.sub.2d] and [v.sub.1c] denote differential input voltage, the differential output voltage
, and the common-mode input voltage, respectively.
The bias voltage [V.sub.b] should be chosen to provide enough voltage swing capability at the SF output; however, it does not need to be accurately controlled, as any error in [V.sub.b] will translate to a common-mode signal for the differential SF circuit, which to first order will not influence the differential output voltage
. The two current sources are periodically switched between the MOSFET and the EGFET (chopping technique) in order to average out the error caused by mismatch in their current levels .
This includes support for the expanded set of standard link rates, which includes 1.62, 2.16, 2.43, 2.7, and 3.24Gbps, as well as the capability for a reduced output differential output voltage
swing down to 200mVpp.
According to (11), for differential output voltage
[v.sub.od] it holds
The resulting differential output voltage
[V.sub.OD] constitutes a dominant bit and thus, logic low (Figure 3).
It's possible to connect a desired number of current sources to the either C or D nodes, whereas those, connected to the C node, will be producing a positive differential output voltage
(Vout) whilst those, connected to the D node, will be producing a negative differential output voltage