differential stage

differential stage

[‚dif·ə′ren·chəl ′stāj]
(electronics)
A symmetrical amplifier stage with two inputs balanced against each other so that with no input signal or equal input signals, no output signal exists, while a signal to either input, or an input signal unbalance, produces an output signal proportional to the difference.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.
References in periodicals archive ?
illustrated an implementation of a current-balancing instrumentation amplifier with a single differential stage [28].
Immunophenotypic features of AML-M6b are dependent on the differential stage of the erythroblasts [1,5].
3) A fully differential stage (differential in and out) incorporated at the front end of the amplifier.
What is done in the Ampzilla 2000 is to make use of the common mode feed forward circuit in the first differential stage of the amplifier that we discussed above.
This differential stage provides a maximum OUtPUt power of +4 dBm to a 1 k[Omega] load (4.5 V peak-to-peak).
The [V.sub.B] (CDMA) and [V.sub.IO] (CDMA) bias terminals are generated from the compensation configuration, consisting of [B.sub.1c], [B.sub.2c] and [B.sub.4c] The differential stage, with input CFCTL, provides a current-steering function to enable/disable the bias outputs.
The second stage of the OTA block diagram resembles the symmetrical OTA topology, with current mirrors [M.sub.7]-[M.sub.8] and [M.sub.9]-[M.sub.10] loading the differential stage [M.sub.5]-[M.sub.6].
When considering the speed power product of complex gates, with respect to the speed-power product of a basic inverter, series gating (stacking of differential stages) is obviously a major advantage of Si ECL technologies.
CML-ECL: Originally, the expression current mode logic (CML) had been coined to describe the logic gate arrangement achieved by stacking differential stages (series gating).

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