Moreover, the dielectric formula can be engineered for the exact thermal conductivity needed to maintain the

emitter junction at the desired operating temperature, within the desired maximum size and weight.

The variation of the space-charge capacitances under applied voltage will depend upon impurities distribution dQ = [eN.sub.D][x.sup.+] = e[N.sub.A][x.sup.-] in the locality of the base-

emitter junction, where their density is much greater than that at the base-collector junction, where the input admittance will be [r.sub.bb] in series with a parallel combination of [g.sub.be] with [C.sub.be] (see Figure 2(a)), and the parameter [g.sub.be] increases approximately linearly with [I.sub.E], being constant with the operating frequency at the biasing condition empirically given by [g.sub.be] [approximately equal to] [V.sub.CE][([V.sub.BE]).sup.-1] gm, where [V.sub.CE] and [V.sub.BE] are voltages under ON characteristics [17].

For

emitter junction of n-p-n integral transistors, as an example, the current density can reach 100 A/[mm.sup.2] and more [7].

Unfortunately, the forward voltage drop of the additional

emitter junction adds to the on-voltage so that even in a package such as DPAK the typical on-voltages achievable are >1.8V, and may reach 2.8V.

By applying of equation (2) for emitter junction, the collector current of the transistor operating in the forward active mode can be presented as follows

where [beta] is the forward current gain and [r.sub.b] is the base series resistance of the transistor, [U.sub.BE] is the voltage applied across the base-emitter and [V.sub.Be] is the potential barrier of the emitter junction. Equation (3) is the base for the derivation of the equation of the input offset voltage.

With a constant voltage base bias, a decrease in the turn-on voltage of the emitter junction causes an increase in collector current.

The decrease in the emitter junction turn-on voltage can be accounted for by adding a temperature-dependent base voltage source

To overcome the base sheet resistance limitation, the emitter width of a Si BJT must be reduced to minimize the base current crowding effect.[3] Therefore, a fine lithography pitch must be utilized or a higher [C.sub.cb] per

emitter junction area will result.

The saturation resistance results primarily from the need for a finite collector voltage to reverse bias the collector-base junction when the base

emitter junction is forward biased.

Linearity may be further improved by negative feedback, and emitter ballast resistors are used to perform an additional duty, for example, the task of linearizing the current voltage relationship of the base to

emitter junction that provides almost all the nonlinearity in an HBT.

Furthermore, the strain due to the lattice mismatch may be used to improve the hole mobility in the base parallel to the

emitter junction. One of the most promising growth techniques for Si/SiGe/Si npn heterojunctions uses rapid thermal chemical vapor deposition.