external interrupt

external interrupt

[ek¦stərn·əl ′int·ə‚rəpt]
(computer science)
Any interrupt caused by the operator or by some external device such as a tape drive.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.

external interrupt

An interrupt caused by an external source such as the computer operator, external sensor or monitoring device, or another computer.
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References in periodicals archive ?
The AT89S52 includes four programmable ports, two external interrupt sources, three timers or counters, one programmable serial USART, 8 kB of program memory, and 256 B of RAM for data.
If an external interrupt source is not available, it is possible to calculate and predict the PWM pulse-centers on an FPGA and send an interrupt to the main processor.
STMicroelectronics said that the FC30, a 14-pin LGA device measuring 3 x 5 x 0.9mm, has a low power drain (together with an external power-down control) and three external interrupt lines, making it a candidate for installation in portable devices requiring applications such as portrait/landscape recognition.
Once a valid external interrupt is recognized by the CPLD, it will determine if it contains the functionality to process the interrupt.
There are also 4 pins that can be configured as chip-select, external interrupt trigger or GIO.
Depending on the power management scheme used, a decrementer interrupt, SMI, or external interrupt (EI) invokes the interrupt handler routine.
Further on in this paper, we are describing the waveforms in the case when the scheduler responds to the occurrence of an asynchronous external interrupt. The setting of the ExtIntEv[0] signal generated by Vivado simulator and the answer of the scheduler can be observed by activating the high priority sCPU0 to which the event is attached.
In this case, 4 sCPUs are presented with TRi registers and 4 external interrupts. The values in Fig.
for n agent's external interrupts of equal priorities):
The architecture of the XC167CI-16F40F has been optimized for high instruction throughput and minimum response time to external interrupts. Intelligent peripheral systems have been integrated to reduce the need for CPU intervention.

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