feature size

The size of the elements on a chip, which is designated by the "DRAM half pitch." The smallest feature size is generally smaller than the feature size for a technology generation (technology node). For example, the 180 nm technology generation will have gate lengths smaller than 180 nm. See DRAM half pitch and process technology.

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Photonic crystals that block infrared and visible light are difficult to make because of the small feature size required.

Holey device traps light for lasers, filters

What are the minimum feature size capabilities of different printing processes?

Research and Markets: Conventional Printing Processes for Functional Devices: Explore where we currently stand and how we push the limits on feature size in printing functional devices

All systems enable typical feature size from several micrometers to less than 50 nanometers with aspect ratios approaching 100:1.

Jenoptik Mikrotechnik Introduces HEX 04 Hot Embossing/Imprinting Equipment; Industry Pioneer's Equipment Enables Micro and Nanotechnogy Part Production for High Volume Applications

Samsung's launch of a flash memory at the 70nm technology node marks the first time that DRAM has been surpassed as the device type with the smallest feature size.

Samsung 73nm NAND Flash Recognized as Most Innovative Process

CAD filtering through feature size is also implemented in Icepro 4.

Fluent Inc. Announces the Latest Release of Icepro 4.1 its CAD Conversion Tool

With the most widely pursued planar FeRAM cell concepts, only structural cell sizes down to approximately 10F-squared are achievable, with F being the minimum feature size of the process.

Infineon Presents Cutting Edge Research Results in Non-Volatile Memory Technologies

The next TwinFlash technology node with feature sizes of only 110nm is being developed to further improve cost position and to enable larger densities of up to 2Gbit.

Infineon enters flash memory market--512Mbit flash chip introduced

As feature sizes in microelectronic components continue to shrink, the stresses associated with the earliest stages of film growth raise serious concerns in the industry about device performance and reliability.

In situ stress measurements during electrodeposition of thin films studied

of Wisconsin, Madison, have developed a technique dubbed "bright-peak technology" for creating 20-nm chip feature sizes with 100-nm masks.

Bright-peak technology blazes ahead. (Micro/Nano Technology)

The SCORR process has been shown to be effective at cleaning feature sizes down to the seven-micron level, which is the benchmark for the industry.

Scorr one for the environment. (Innovations)

As the lateral feature sizes of complementary metal oxide semiconductor field-effect-transistors are scaled downward, the gate dielectric capacitance must be increased in order to maintain the same drive current.

NIST/SEMATECH collaboration leads to breakthrough on interface state density extraction

18um process technology and soon will be offered in smaller feature sizes.

Mixel Showcases the Newest Members of Its SerDes IP Family, Quad 1.25Gbps/Channel LVDS Serializer and De-Serializer at DesignCon2007