# floating-point arithmetic

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Related to floating-point arithmetic: floating-point notation, Floating point value

## floating-point arithmetic

[¦flōd·iŋ ¦pȯint ə′rith·mə·tik]
(mathematics)
A method of performing arithmetical operations, used especially by automatic computers, in which numbers are expressed as integers multiplied by the radix raised to an integral power, as 87 × 10-4 instead of 0.0087. Also known as floating arithmetic; floating-decimal arithmetic.
References in periodicals archive ?
12], The proposed algorithm uses the binary64 floating-point arithmetic and produces at each iteration a block of 32 random bits.
Like the PLC 5 before it, the Allen-Bradley ControlLogix PAC can handle floating-point arithmetic.
For more information on binary floating-point arithmetic and the IEEE standard we refer the reader to [17, 23, 24, 26].
The use of floating-point arithmetic often provides enhanced performance due to the large dynamic range and greatly simplifies the task of system performance verification against a floatingpoint simulation.
As can be seen below, the correct answer is never found even as the number of bits used in the floating-point arithmetic to calculate the solution increases from 32- to 64- and finally 128-bits of precision:
Hardware support (as opposed to exclusive software support) for floating-point arithmetic became widely available only after the IEEE published floating-point format standards.
ColdFire MCF5272 is a RISC-architecture processor with the following features among others: big-endian integer representation, no floating-point arithmetic, and no MMU.
The IEEE standard [IEEE 1985] for floating-point arithmetic, which became official in 1985 and which we shall refer to as IEEE-754, has been adopted by most major microprocessor manufacturers.
First, in floating-point arithmetic, multiplication is simpler than addition and subtractions in that it does not require shifting an operand to align them before performing the computation.
ANSI/IEEE-1985 Standard for binary floating-point arithmetic, IEEE, Piscataway, N.
It is a 49-circuit-card design based on 22-bit floating-point arithmetic, using commercially available VLSI circuit elements with a total dissipation of 5.

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