One is responsible for the adder's architecture implemented with the one-bit full adder as a building block.
We have analyzed and compared the most interesting known topologies to implement a 10T full adder and 14T full adder.
In this paper different components have been combined to make new 16T, 14T and 10T full adder cells.
The Full adder which is the fundamental unit of the arithmetic unit.
The Figure 4 shows the Schematic configuration of the full adder cell consists of 14 Transistor that ensures both low power and high speed performance.
System speed takes a hit, therefore to ensure better speed performance a fast full adder has been designed and it consists of 16 Transistors shown in Figure 3.
Another schematic configuration of the full adder cell consists of 10 Transistor that ensures both low power and high speed performance.
The Figure 6 and Figure 7 shows the T-spice output waveform of 20T and 16T Full Adder cell respectively.
In this paper we have carried out a comparison among the most suitable topologies of full adder, including recently proposed ones.