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see viperviper,
any of a large number of heavy-bodied, poisonous snakes of the family Viperidae, characterized by erectile, hypodermic fangs. The fangs are folded back against the roof of the mouth except when the snake strikes. Vipers are distributed throughout Eurasia and Africa.
.

an analogue computing device whose output represents a quantity that is proportional to the sum of the input quantities, or signals. Mechanical adders are used primarily for the summing of displacements. The slide rule, for example, can be classed as a mechanical adder; it sums linear displacements. The differential gear is a mechanical adder that sums angular displacements. In electromechanical adders, the input and output quantities are mechanical displacements, and summation is carried out through use of the principles of electric circuits, particularly Kirchhoff’s laws. Electrical adders sum currents or voltages. The most common types of adders used in electronic analogue computers sum currents. To increase accuracy and raise the power and amplitude of the output signal, such adders are supplemented by operational amplifiers (seeCOMPUTING AMPLIFIER).

the basic component of the arithmetic unit of a digital computer. Adders are used to peform the operation of addition of numbers.

When decimal numbers are added digit by digit, the digits in the units digit place in the addends are added first. If the result is a one-digit number, it is entered in the units place of the final sum. If the result is a two-digit number, only the digit in the units place of this number is entered in the units place of the sum; the tens are carried—that is, the digit in the tens place is added to the digits in the tens places of the original addends. The addition operation is then carried out on the tens digits. The process is repeated for the higher order digits until the final sum is obtained. As an example, let us consider the addition of 157, 68, and 9. The digits 7, 8, and 9 are added first. Since the result is the two-digit number 24, the 4 is entered in the units place of the final sum, and the 2 is carried. The sum of 2, 5, and 6 is 13. The 3 is entered in the tens place of the final sum, and the 1 is carried. Since the sum of 1 and 1 is 2, the digit in the hundreds place in the final sum is 2. The final sum is thus 234.

When binary numbers are added digit by digit, the same process is used. The digits in the given digit place in the addends are summed, and to this result there is added the carry, if any, from the next lower place. Following the rules of addition in the binary number system, we thus obtain the digit in the given place of the final sum and the carry to the next higher place. Figure 1. Schematic of a half-adder: (x) and (y) addends, (S) sum, (c) carry to next higher digit place

Table 1. Inputs and outputs of a half-adder
InputsOutputs
xySc
0000
1010
0110
1101

A number of different circuit designs and combinations of elements are used in adders. The various types of adders differ in the following ways: number system used (for example, binary adders, decimal adders, and binary coded decimal adders), number of inputs (two-input and three-input), manner of handling multidigit numbers (serial, parallel, and serial-parallel), manner

Table 2. Inputs and outputs of a three-input adder
InputsOutputs
xiYiCi – 1SiCi + 1
00000
00110
01010
01101
10010
10101
11001
11111

of organizing the summation process (combinational and accumulating), and manner of organizing the carry circuits (sequential carry, ripple-through carry, group carry, and simultaneous carry). The type of adder chosen for a particular purpose depends primarily on the system of elements used in the computer and on the speed and economy requirements. Speed is one of the most important parameters of an adder. For the sake of speed in arithmetic operations, third-generation computers use not single-digit adders but group adders, which rapidly calculate the sums and carries for a group of digit places. Figure 2. Schematic of a three-input adder consisting of two half-adders and an OR gate: (HA) half-adder, (xi) and (yi) addends, (ci – 1) carry from next lower digit place, (Si) sum, (ci + 1) carry to next higher digit place

Besides the basic operation of addition, most adders are also used for multiplication, division, and various logical operations, such as logical addition and logical multiplication.

### REFERENCES

Kartsev, M. A. Arifmetika tsifrovykh mashin. Moscow, 1969.
Kagan, B. M. and M. M. Kanevskii. Tsifrovye vychislitel’nye mashiny i sistemy. Moscow, 1973.
Presnukhin, L. N. and P. V. Nesterov. Tsifrovye vychislitel’nye mashiny. Moscow, 1974.

L. N. STOLIAROV

(computer science)
A computer device that can form the sum of two or more numbers or quantities.
(electronics)
A circuit in which two or more signals are combined to give an output-signal amplitude that is proportional to the sum of the input-signal amplitudes. Also known as adder circuit.
(vertebrate zoology)
Any of the venomous viperine snakes included in the family Viperidae.

1
1. a common viper, Vipera berus, that is widely distributed in Europe, including Britain, and Asia and is typically dark greyish in colour with a black zigzag pattern along the back
2. any of various similar venomous or nonvenomous snakes

2
a person or thing that adds, esp a single element of an electronic computer, the function of which is to add a single digit of each of two inputs

An elementary electronic circuit that adds the bits of two numbers together.
References in periodicals archive ?
"Novel 10-T full adders realized by GDI structure", Integrated Circuits 2007.
Sarkar, "Transistor Count Optimization of Conventional CMOS Full Adder & Optimization of Power and Delay of New Implementation of 18 Transistor Full Adder by Dual Threshold Node Design with Submicron Channel Length", International Conference on Computers and Devices for Communication, pp.
The complementary CMOS full adder (C-CMOS) as shown in Fig.
One is responsible for the adder's architecture implemented with the one-bit full adder as a building block.
Table I: Various logic functions of GDI cell for different input configurations N P G Out Function 0 B A A'B F1 B 1 A A'+B F2 1 B A A+B OR B 0 A AB AND C B A A'B+AC MUX 0 1 A A' NOT Table II: Comparison of Full adders. FULL CMOS 32 nm ADDER Power (mW) Delay (ps) PDP Design 1 0.706 991.6 8.17 E-15 Design 2 1.05 990.68 5.60 E-15 Design 3 0.810 999.99 6.65 E-15 FULL FinFET 32 nm ADDER Power Delay PDP ([micro]W) (ns) Design 1 0.373 5 1.84 E-15 Design 2 0.407 4.86 1.98 E-15 Design 3 0.406 4.98 2.02 E-15
Reduction is performed using a full adder or a half adder depending on the number of elements in that particular column of the group.
First and second design of reversible 4:2 compressor in  is based on using MKG and HNG as reversible full adders. Because the MKG gate has quantum cost larger than HNG gate, clearly the quantum cost of second design is less than first design.
(ii) Design of cost-effective full adder based on proposed 5-input majority gate.
Simulations were conducted for both symmetric and asymmetric FinFETs based transmission gates full adders. Results shown in Table 8 indicate that using asymmetric work functions reduces leakage current by a factor of 6 with a 7% improvement in delay compared to symmetric counterpart device.
In this design, FinFET based 4-2 compressor and full adders are used to reduce the partial product stage.
Case Study on a 64-Bit Full Adder. We implemented a 64-bit full adder using CMOS and DCVSL in Cadence Virtuoso.
As when all the inputs to the full adders are low, then the outputs are also low values.

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