hole mobility

hole mobility

[′hōl mō‚bil·əd·ē]
(electronics)
A measure of the ability of a hole to travel readily through a semiconductor, equal to the average drift velocity of holes divided by the electric field.
References in periodicals archive ?
When properly engineered, such polymer blends display a temperature-insensitive charge transport behavior with hole mobility exceeding 2.0[cm.sup.2] /V-s across a wide temperature range from room temperature up to 220[degrees]C in thin-film transistors.
The transport characteristics of the P2 samples revealed us a considerable enhancement of the hole mobility. The current measured in P2-based FETs was about a factor of 3 greater when compared with P1-based transistors.
Electron mobility and hole mobility are calculated with MATLAB software and input into AFORS-HET for simulation.
Hole mobility is adversely affected in donor-acceptor composite films, as thin film coating technique such as spin coating on account of fast solvent evaporation do not support well-organized growth of P3HT crystals [8].
Material GaAs [A.sub.l0.8] [Ga.sub.0.2]As Band Gap(eV) 1.42 [10] 2.09 [11] Electron affinity (eV) 4.07 [10] 3.53 [11] Dielectric permittivity(relative) 13.18 [10] 10.68 [11] Eelectron mobility ([cm.sup.2]/Vs) Varied [12] 212 [13] Hole mobility ([cm.sup.2]/Vs) Varied [12] 67 [13] Radiative recombination coefficient 7.20E-10 [10] 7.50E-10 [11] ([cm.sup.3]/Vs) Lattice constant a(A[degrees]) 5.65 [10] 5.64 [13] Absorption coefficient Data from [14] Data from [11] Fig.
By demonstrating that they can achieve high hole mobility in trigate transistors, Hoyt and her team have also shown that their approach will remain useful in the chips of the future.
When the acceptor impurity band exists in the films, the mobility [[mu].sub.p] is related to the hole mobility in the valence band [[mu].sub.v] and the mobility in the impurity band [[mu].sub.i] which was reported by Emelyanenko et al.
But PVK has, however, an inherent defect in that its electron and hole mobility difference are too large [16].
Cost-effective process-induced stress techniques were used to enhance electron and hole mobility. By optimizing shallow trench isolation (STI) stress, sidewall stress, and silicon nitride (SiN) stress on the gate, it was possible to improve the performance of both NMOS and PMOS.
IBM has been able to integrate devices with 2.5 times higher hole mobility into conventional CMOS technology by combining two substrates in the same wafer.
His studies of defects that a silicon germanium layer has on a silicon lattice led to published papers demonstrating an 80% enhancement in electron mobility in NMOS devices and a 40% acceleration of hole mobility in PMOS devices.