HyperTransport


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HyperTransport

A high-speed interconnection architecture between integrated circuits, introduced in 2001. Code-named Lightning Data Transport and developed by AMD and others, the HyperTransport I/O Link Specification defines a protocol and electrical interface between the CPU, memory and peripheral devices.

Since its introduction, HyperTransport's maximum aggregate bandwidth of 32-bit links progressed from 12.8 to 41.6 Gbytes/sec. Version 3.0 also added dynamic link splitting under software control. Called "Un-Ganging," it enables a single unidirectional link to be split into two; each at half the original bit width. HyperTransport (HT) was designed to be fully compatible with legacy PCI (running at 33 or 66 MHz) plus PCI Express and PCI-X technologies. For more information, visit the HyperTransport Consortium at www.hypertransport.org.
HYPERTRANSPORT VERSION               HT 1.x   HT 2.0   HT 3.0Feature        (2001)   (2004)   (2006)

 Clock speed    800 MHz  1.4 GHz  2.6 GHz

 Bandwidth
  (GB/sec)       12.8     22.4     41.6

 Hot pluggable   No       No       Yes

 Un-Ganging      No       No       Yes
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General detailsCo New ZOTAC GeForce 8100Co High-performance value platformCo NVIDIA GeForce 8100 graphics processorCo AMD dual, tri and quad-core Phenom, Athlon and Sempron compatibleCo Socket AM2+Co HyperTransport 3.0Co MicroATX form factorCo PCI Express 2.0 x16 expansionCo DirectX 10 with Shader Model 4.0 compatibleCo NVIDIA Hybrid SLI readyCo NVIDIA GeForce Boost readyCo NVIDIA HybridPower readyCo Six-channel high-definition audioCo 10/100 EthernetCo DVI and VGA output
There are another dozen communications processors that link to the HyperTransport buses on the Opterons to provide a high-speed link to the switching fabric that connects all of the shelves in a massively parallel machine to each other.
-- Dual AMD Opteron Processor 200 Series - CPU Built-in 1MB L2 cache -- Three HyperTransport links providing up to 19.2 GB/s peak bandwidth per processor -- 128-bit Dual Channel Memory Controller - Integrated in CPU -- Simultaneous 32- and 64-bit computing capability
La tecnologia HyperTransport ayuda a reducir el numero de buses, al mismo tiempo que provee una liga de alto rendimiento para PCs, estaciones de trabajo y servidores, asi como para numerosas aplicaciones integradas y sistemas de multiprocesos altamente escalables.
In addition, AMD HyperTransport 3.0 technology (HT3) increases interconnect rates from 2 gigatransfers per second (GT/s) up to a maximum 4.8GT/s.
General details* New ZOTAC GeForce 8100* High-performance value platform* NVIDIA GeForce 8100 graphics processor* AMD dual, tri and quad-core Phenom, Athlon and Sempron compatible* Socket AM2+* HyperTransport 3.0* MicroATX form factor* PCI Express 2.0 x16 expansion* DirectX 10 with Shader Model 4.0 compatible* NVIDIA Hybrid SLI ready* NVIDIA GeForce Boost ready* NVIDIA HybridPower ready* Six-channel high-definition audio* 10/100 Ethernet* DVI and VGA output
The buses and protocols addressed include CAN, SPI, RS-232, SATA, SAS, PCIe, FibreChannel, Serial Rapid 10, and HyperTransport.
These needs are driving the adoption of new processor interconnect standards such as Intel's common system interface (CSI) and AMD's HyperTransport. In the future, it makes sense to avoid that bus.
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InfiniPath is the industry's lowest latency Linux cluster interconnect, delivering SMP-class performance to commodity-priced Linux clusters while leveraging important standards such as HyperTransport technology, InfiniBand, MPICH and AMD64 Direct Connect Architecture.
Several popular bus standards, including HyperTransport, RapidlO, and PCI Express, have evolved to support switch-based interconnects.
With this exceptional flexibility, the Hydra core supports a number of standards and data rates including, but not limited to Gigabit Ethernet, SGMII, XAUI, CX-4, Serial RIO, Parallel RIO, SFI4.1, SPI4.2, SPI5, and HyperTransport. The unique in-system selectable LVDS and PCML I/Os allow the design of single ports that support both LVDS-based and PCML-based interfaces such as SPI4.2 (LVDS) and XAUI (PCML).