instruction prefetch


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instruction prefetch

(architecture)
A technique which attempts to minimise the time a processor spends waiting for instructions to be fetched from memory. Instructions following the one currently being executed are loaded into a prefetch queue when the processor's external bus is otherwise idle. If the processor executes a branch instruction or receives an interrupt then the queue must be flushed and reloaded from the new address.

Instruction prefetch is often combined with pipelining in an attempt to keep the pipeline busy.

By 1995 most processors used prefetching, e.g. Motorola 680x0, Intel 80x86.

References in periodicals archive ?
As we see in Figure 3(b), the prefetch address of a pf_d instruction prefetch is known immediately after the Decode stage (the other three prefetch types would require some additional time), while the address for a data prefetch is not known until it is computed in the Address Calculate stage.
The 20Kc features a seven-stage pipeline with instruction prefetch and dynamic branch prediction, an integrated MMU, and 32 kbytes each of 4-way set-associative instruction and data cache.