instruction set architecture


Also found in: Acronyms.

instruction set architecture

(architecture)
(ISA) The parts of a processor's design that need to be understood in order to write assembly language, such as the machine language instructions and registers. Parts of the architecture that are left to the implementation, such as number of superscalar functional units, cache size and cycle speed, are not part of the ISA.

The definition of SPARC, for example, carefully distinguishes between an implementation and a specification.
References in periodicals archive ?
[10] propose a new instruction set architecture and a register allocation optimized for this architecture.
Many modern commercial microprocessors also have SIMD capability, which has become an integral part of the Instruction Set Architecture (ISA).
The machine description files contain information of the instruction set architecture (ISA), the application binary interface (ABI), and the processor model of the target architecture.
Modern MCUs, such as the Renesas RXFamily of 32-bit MCUs, have an instruction set architecture that contains dedicated notes for DSP and floating-point math that enable fast and efficient processing of those tasks.
The DesignWare ARC EM4 and ARC EM6 are the first processor cores to be built with the new ARCv2 instruction set architecture (ISA) and pipeline.
This technology consists of the Multi-Thread Virtual Pipeline parallel computing core, an independent instruction set architecture (ISA), an optimizing compiler and the Agile Switch dynamic load balancer.
Sizzling demands for smartphones and tablet PCs since last Christmas shopping season are prompting these chip vendors to increase supplies of application processors designed for these mobile gadgets around the 32-bit ARM instruction set architecture.
The Nios II family of embedded processors consists of three processor cores that implement a common instruction set architecture, each optimized for a specific price/performance point, and all supported by the same software tool chain.
The ARM1136J-S and the ARM1136FJ-S microprocessor cores feature a combination of high performance, low power, small size, high code density and powerful instruction set architecture to target next-generation, high-volume products across a broad range of market applications.
Metrowerks simplifies and speeds application development for Motorola systems containing the PowerPC instruction set architecture (ISA), with the release of CodeWarrior Development Studio, PowerPC ISA Edition for Communications Processors, Version 8.
The Itanium will move Intel (and presumably the rest of the PC industry, where Intel chips still rule) to a completely new instruction set architecture. Moving from the decade-old 32-bit, x86 instruction set to 64 bits will require an enormous investment in time and developer manpower; Intel is clearly betting that both software developers and hardware OEMs will make the commitment.

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