MegaChips took advantage of the ultra-low power Xtensa processor architecture, which can perform both control and digital signal processing (DSP), customizing it for maximum throughput with three-way very long instruction word
(VLIW) processing, floating point, and four-way single instruction, multiple data (SIMD) processing.
The Very Long Instruction Word
-- Single Instruction Multiple Data (VLIW-SIMD) DSP architecture delivers breakthrough performance and low power consumption.
It is equipped with 1 MByte internal RAM and has a Very Long Instruction Word
Key changes include a complete rewrite of the code morphing software which feeds instructions to the architecture's Very Long Instruction Word
A Crusoe processor uses a Very-Long Instruction Word
(VLIW) instruction set at its core; CM software is responsible for the translation of x86 instructions to VLIW so that they can be processed by the CPU.
A question that immediately comes to mind is: what fundamentally new techniques of the same importance as pipe-lining, superscalar, and very long instruction word
(VLIW) are being proposed today for use in processors 10 years from now?
The first programmable very long instruction word
processor (VLIW), the TM-1 will have sound, music, video, and graphics capabilities.
Further on down the line look for Intel and Hewlett-Packard to release a Very Long (or Large) Instruction Word
(VLIW) 64-bit CPU in 1997 or 1998.
1) An increase from 8 to 16 bits in the data processing capabilities of the 128 processing engines, as well as an increase from four to six instructions in the variable-length instruction word
(VLIW) to enable faster processing speeds
Enhancements in flexible length instruction extensions (FLIX) for Xtensa LX6 that allow for very long instruction word
(VLIW) instructions of any length from 4 to 16 bytes, resulting in code size savings of up to 25 percent compared to prior Xtensa versions, thus enabling local memory and cache size reductions of up to 25 percent for the same performance level.
TRIPS includes a new "block-oriented execution" scheme that sounds suspiciously like the very long instruction word
(VLIW) processing techniques that IBM's supercomputing gurus have been playing around with since the mid-1980s.
Its key features include: Support for four 32x32-bit multiplier-accumulators (MACs) per cycle with 72-bit accumulators, more than double the performance of other audio DSPs for computationally intensive functions such as fast Fourier transform (FFT) and finite impulse response (FIR), Support for eight 32x16-bit MACs per cycle under specified conditions, Four very long instruction word
(VLIW) slot architecture capable of issuing two 64-bit loads per cycle, Optional vector floating-point unit available, providing up to four single-precision IEEE floating-point MACs per cycle, Software compatible with the existing HiFi DSP family consisting of over 140 HiFi-optimized audio and voice codecs and audio enhancement software packages.