interrupt latency


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interrupt latency

The time it takes to service an interrupt. It becomes a critical factor when servicing real-time functions such as a communications line. See UART overrun.
References in periodicals archive ?
High performance, combined with an ARM Cortex-M7 core, results in an interrupt latency as low as 20 nanoseconds the lowest among all ARM Cortex-based products.
The interrupt latency and context switching represent characteristics typical to the nMPRA processor, these coefficients having acceptable values for a deterministic architecture [15].
When engineers think about using a real-time operating system they worry about task timing, interrupt latency, and other timing- and task-related concerns.
4 shows that interrupt latency takes a bit more time because of the hardware response and the ISR execution that happens before the context switch to the new task that will serve the external request.
It offers advanced features that are optimised for MCU and real-time embedded applications, including reduced interrupt latency, flash acceleration, debug features including iFlowTrace and support for AHB Lite as the interconnect interface.
Actually, there are four elements that contribute to the overall delay between an interrupt and the time the associated application program starts to run: interrupt latency, interrupt handler duration, scheduler latency, and scheduling duration.
Events that incur more than six cycles of latency can mask the interrupt latency. For example, instruction cache misses usually take long enough that the interrupt is delivered to the processor before the instruction that incurred the IMISS has issued.
The latency figures include interrupt latency, that is the receiver does not poll the network device.
An interrupt latency is the time it takes a CPU to service a hardware interrupt generated by a plug-in board.
We have also considered the interrupt latency which is 12 clock cycles for the fast interrupt (FIQ) and 25 clock cycles for ordinary interrupt (IRQ) [33].
These new MCUs introduce and expand the offering of Microchip s Core Independent Peripherals (CIP), which were designed to reduce interrupt latency, lower-power consumption and increase system efficiency, and safety, while minimizing design time and effort.
The superscalar SH-2A CPU core exhibits 2 DMIPS/MHz performance and interrupt latency of six cycles.