level-sensitive scan design

level-sensitive scan design

(circuit design) (LSSD) A kind of scan design which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held low during system operation but cause the scan data to be latched when pulsed high during scan.

____ | | Sin ----|S | A ------|> | | Q|---+--------------- Q1 D1 -----|D | | CLK1 ---|> | | |____| | ____ | | | +---|S | B -------------------|> | | Q|------ Q2 / SOut D2 ------------------|D | CLK2 ----------------|> | |____|

In a single latch LSSD configuration, the second latch is used only for scan operation. Allowing it to be use as a second system latch reduces the silicon overhead.
References in periodicals archive ?
The requirements included the ability to optimize the coexistence of IBM's level-sensitive scan design (LSSD) structures with LogicVision's BIST structures, unique clocking techniques and special pads, to name a few key examples.
Every one of these designs used IBM's level-sensitive scan design (LSSD) test methodology, which ensures complete testability of chips with minimal impact on die area and system performance.