linear address space

linear address space

A memory addressing scheme used in processors where the whole memory can be accessed using a single address that fits in a single register or instruction. This contrasts with a segmented memory architecture, such as that used on the Intel 8086, where an address is given by an offset from a base address held in one of the "segment registers". Linear addressing greatly simplifies programming at the assembly language level but requires more instruction word bits to be allocated for an address.
Mentioned in ?
References in periodicals archive ?
The microcontroller leverages a Harvard architecture with 16-bit index registers and stack pointer, a 16Mbyte linear address space, advanced addressing modes, and other features designed to optimally support C-programming to deliver leading-edge CPU performance in both speed and code density.
This function comprises a 16-bit interface bus and two SRAM banks each with a 1 KB linear address space, providing for direct reading and writing from the main microprocessor by access to this SRAM.

Full browser ?