linear address space

linear address space

A memory addressing scheme used in processors where the whole memory can be accessed using a single address that fits in a single register or instruction. This contrasts with a segmented memory architecture, such as that used on the Intel 8086, where an address is given by an offset from a base address held in one of the "segment registers". Linear addressing greatly simplifies programming at the assembly language level but requires more instruction word bits to be allocated for an address.
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flat address space

Memory (RAM) that is addressed starting with 0, and each subsequent byte is referenced by the next sequential number (1, 2, 3, etc.). A 32-bit computer with a 32-bit address space treats all 4GB of memory (its maximum) as one contiguous segment. However, a 64-bit address register can hold a gigantic number, and 64-bit motherboards limit the maximum memory typically to 128GB (see binary values).

In contrast, the 16-bit mode (Real Mode) in an x86 PC uses a segmented address space. Memory is broken up into 64KB segments, and a segment register is always being adjusted to point to the base of the segment that is currently being addressed. See Real Mode and address register.
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This function comprises a 16-bit interface bus and two SRAM banks each with a 1 KB linear address space, providing for direct reading and writing from the main microprocessor by access to this SRAM.

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