little-endian

little-endian

(data, architecture)
A computer architecture in which, within a given 16- or 32-bit word, bytes at lower addresses have lower significance (the word is stored "little-end-first"). The PDP-11 and VAX families of computers and Intel microprocessors and a lot of communications and networking hardware are little-endian.

The term is sometimes used to describe the ordering of units other than bytes; most often, bits within a byte.

Compare big-endian, middle-endian. See NUXI problem.
References in periodicals archive ?
The next day was going to be a big day: Citizens of Bitotia would once and for all establish which byte order was better, big-endian (B) or little-endian (L).
Assuming the data can be found, and the appropriate word substituted where necessary, the operating chip will need to know if the word is bigendian or little-endian. The byte stream is described as little-endian when the low-order byte of the number is stored in memory at the lowest address, and the high-order byte at the highest address; big-endian is the reverse.
Compaq joined the Monterey64 initiative "because it might lead to a unified Unix on Intel," Pfeiffer said, "like we have a single NT on Intel." Sun Microsystems Inc (little-endian Solaris x86), Silicon Graphics Inc and Hewlett-Packard Co (big-endian Irix and HP-UX on IA-64 respectively) still stand opposed.
Our implementation of r1mach and d1mach recognizes big- and little-endian IEEE, Vax D and G, IBM mainframe, Cray 1, T3E, and Convex C-1 formats, with possible compiler autodoubling.
Furthermore, the architecture allows storage references to follow either a big-endian or a little-endian byte ordering convention.
For example, the Motorola NT compiler must target a little-endian environment that requires CodeView symbolic debugging information, whereas the Motorola C and Fortran compilers for AIX systems use big-endian, XCOFF conventions and a STAB-style debugging format.
This mode can be dynamically switched and specifies that the little-endian transformation applies to both instructions and data.
Little-endian byte addressing and VAX/IEEE floating-point are carried over from the VAX and MIPS architecture customer bases.(1) We assumed that most implementations would pipeline instructions (i.e., they would start execution of a second, third, etc., instruction before the execution of a first instruction completes).
Alpha AXP implementations are bi-endian, allowing data to be accessed using either a little-endian view (byte 0 is the low byte of an integer), or a big-endian view (byte 0 is the high byte of an integer).
Example 1 in Figure 4 shows a 2-instruction sequence for loading a byte into the low end of a register, using little-endian byte numbering.
In the C300 version, CLIPPER can function in either a little-endian or big-endian mode, although internally the little-endian-ness is retained.