puts you in control of a huge mechanical monster that has a human consciousness.
negative requirements) of deadlock and livelock
Note that the net may be unsound if it contains a deadlock (a nonterminal marking where there are not enough resources to proceed any further even with one single step) or a livelock
(there are always enough resources to make a following step, but all possible steps are not "progress"-steps, i.
Mogul and Ramakrishan  describe a system that uses interrupts under normal network load and polling under overload, in order to avoid receiver livelock
Routing algorithms that route packets along the set of channels identified in Step 1 and use only the turns from one set to another allowed by Steps 4 through 6 are deadlock free, livelock
free, and highly adaptive.
SolidAC is a subset of Solidify, containing a module browser, RTL compilers, source code debugger and waveform display, and a set of automatic checks such as dead code, deadlock, livelock
, clock crossing, constant signals, FSM checks, X propagation issues, array over-bound, reset, tri-state buses, and pragma.
- Opposite of deadlock, where someone is blocked from finishing a task.
In addition, Click processed packets at a lower priority than interrupts, leading to receive livelock
[Mogul and Ramakrishnan 1997]: with increasing numbers of input packets, interrupt processing eventually starved all other system tasks, leading to reduced throughput.
Jade programmers need not deal with the complex phenomena such as deadlock, livelock
, and starvation that characterize explicitly parallel programming.
Problems such as deadlock and livelock
among processes are completely hardware independent.
Both Saphirus and CMR Design Automation will sell the complete Solidify line, which includes the Solidify property checking engine, SolidAC[TM] for automated checking of common design issues such as clock domain crossing, dead code, finite state machine (FSM) deadlock and livelock
, case statement pragmas, reset propagation, bus contention, X assignment propagation, and array out-of-bounds, and SolidPC[TM] for AMBA protocol verification.
Any purely interrupt-driven system using fixed interrupt priorities will suffer from receive livelock
under input overload conditions.