The Table 7 shows the confusion matrix for classification of laminated calcareous rock, applying the

logic function to remaining sections not classified for the SVMs and photoelectric factor [greater than or equal to] 4, in this case the error increased from 5.38% to 48.17%.

As the merging parallel transistors, IG FinFET can also work as merging series transistors when the threshold voltage is modulated to high enough, so that high threshold IG FinFET can realize the AND-like

logic function of the inputs from the two gate electrodes [2].

The collective behavior of the studied nanosystems presents potential applications to perform all-optical encryption by ultrafast XOR

logic functions. In regard to the remarkable nanoscale third-order nonlinear optical effects exhibited by carbon/metal nanoink-based materials, the design of optical platforms fabricated by advanced nanoinkjet systems can be adequate.

Although the above-mentioned [R.sub.0]-function system and [R.sub.1] -function system have the same

logic function, their differential characteristics are various.

The design in Figure (2) can be compared with Figure (1) and both have three sets of LFSR with majority

logic function. the RTL schematic has an addition of Counter submodule which is used to keep track on the number of cycles that has passed.

A wide range of complex

logic functions in which PTL was used, can be replaced by GDI Technique and this makes the circuit simple [4-6].

It consists of a pull-down network (PDN) that implements the

logic function (OUT) as well as its complement (OUTB) using NMOS transistors only.

After configuring FPGA, the specified operation task is performed, and during this period, the

logic function circuit of the FPGA is kept unchanged.

Single

Logic Function. In this section, a single

logic function has been converted into a linear algebraic equation.

The

logic function B x S should be fed to input X and also the inputs A and S should be fed to the inputs Y and Z, respectively.

According to

logic function, the modified circuit is mapped to specified logics.

But from [7] our structure differs in

logic function integration: to reach higher operating frequencies not only AND gates at inputs of D flip-flops but also NAND gate at the output of D flip-flop in end-of-cycle logic block is combined into D flip-flop (Fig.