The digital input receiver compares the incoming signal with a certain threshold, and provides logic high
or low output to a host controller.
Receiver (Rx) inputs feature a "full fail-safe" design, which ensures a logic high
Rx output if Rx inputs are floating, shorted, or terminated but undriven.
For several years, there have been tools called mixed-signal oscilloscopes that can use four input channels with 8-bit ADCs to capture analog-shaped signals using one part in 256 vertical resolution and provide up to 36 lines for capturing digital buses as being either logic high
Rx inputs feature a fail-safe-if-open design, which ensures a logic high
Rx output if Rx inputs are floating.
In this mode, hand selection is accomplished by setting pins FS0/SDEN and FS1/LD to logic HIGH
* Minimum acceptable logic high
voltage--by decreasing the pulse high level
In digital logic mode, the output signal is either logic high
(~VCC) or low (i.e.
But, the series termination resistors we chose to use on all boundary scan pins let pin A on net X both drive and sense a logic high
while simultaneously pin B on net Y drove and sensed a logic low on its side of the short circuit.
frequency constant (frequency programmed) Phase resolution up to 8 bits (1.4 [degrees]) Phase accuracy [+ or -]0.5 LSB or better Insertion loss (dB) (max) 5 Return loss (dB) (min) 14 Digital inputs number of bits 12 + latch logic threshold (V) 2.5 survival level (V) [+ or -]30 logic low current (mA) (max) 0.5 logic high
internal pull up Switching speed ([[micro]second]) typical 2 maximum 5 Mute function (dB) (optional) typical 80 minimum 60 TABLE II BANDWIDTH/RESOLUTION TRADE OFFS Frequency Phase Input Frequency Input Phase Bandwidth Word Length Word Length Resolution Ratio (Bits) (Bits) ([degree]) up to 1.04 8 4 1.40 up to 1.20 7 5 2.81 up to 1.90 6 6 5.62 up to 2.00 5 6 11.25 ADDITIONAL FEATURES
To perform arbitration the protocol defines the two digital logic states on the bus as recessive for logic high
, or a one, and as dominant for logic low, or a zero.
If, during the test for U8, the tester is told to drive pin 4 high, then the driver attached to node N8 temporarily sources enough current to backdrive the output of U3 so a logic high
voltage is achieved on U8 pin 4.
A logic high
selects the CDMA mode while logic low selects the FM mode.