logic low

logic low

[′läj·ik ‚lȯ]
(electronics)
The electronic representation of the binary digit 0 in a digital circuit or device.
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When the front gate is logic low, the back gate is also biased to low voltage, which raised the threshold voltage and reduced the leakage current.
If DBI is enabled, the driver (the controller during a write or DRAM during a read) counts the number of 0s (logic low) bits.
At the same time, the logic low voltage ([V.sub.DD]-[DELTA]V) must be low enough, so that the input NMOS transistor of the next SRMCML circuits can be shut down reliably
The NAND_Out port is pulled down to logic low through NMOS transistors N0, N1, and N2; this in turn activates PMOS transistor P1.
To perform arbitration the protocol defines the two digital logic states on the bus as recessive for logic high, or a one, and as dominant for logic low, or a zero.
* Frequency shift key (FSK) modulation uses two different carrier frequencies to represent the logic high and logic low of digital data.
Referring to Figure 1, if N1 or N2 is a logic low, then the output of U3 will drive node N8 low.
* Maximum acceptable logic low level, by increasing the pulse low level
Output is logic high if signals are in synch or logic low if signals are out of synch, or if one is missing.
frequency constant (frequency programmed) Phase resolution up to 8 bits (1.4 [degrees]) Phase accuracy [+ or -]0.5 LSB or better Insertion loss (dB) (max) 5 Return loss (dB) (min) 14 Digital inputs number of bits 12 + latch logic threshold (V) 2.5 survival level (V) [+ or -]30 logic low current (mA) (max) 0.5 logic high internal pull up Switching speed ([[micro]second]) typical 2 maximum 5 Mute function (dB) (optional) typical 80 minimum 60 TABLE II BANDWIDTH/RESOLUTION TRADE OFFS Frequency Phase Input Frequency Input Phase Bandwidth Word Length Word Length Resolution Ratio (Bits) (Bits) ([degree]) up to 1.04 8 4 1.40 up to 1.20 7 5 2.81 up to 1.90 6 6 5.62 up to 2.00 5 6 11.25 ADDITIONAL FEATURES
When the Enable input pin transitions from logic low to logic high, the device turns ON and starts charging the bucket capacitor.
A logic high selects the CDMA mode while logic low selects the FM mode.