addressed logic synthesis
techniques for engineering change problems .
Perkowski, "Logic synthesis
of reversible wave cascades," in Proceedings of 11th IEEE International Workshop on Logic Synthesis
In the past, BDDs have significantly improved the performance of algorithms and enabled the solution of new classes of problems in areas such as formal verification and logic synthesis
(see, for example, Burch et al.
Synplicity, Inc., Sunnyvale, Calif., a supplier of logic synthesis
, physical synthesis and verification software has announced that its Synplify(R) and Synplify Pro logic synthesis
products include full support for the recently announced Xilinx(R) (Nasdaq:XLNX) Virtex(TM)-II FPGA architecture.
Antrim says it is attempting to take the mystery out of mixed signal design, something logic synthesis
tools did in the digital design world back in the late 1980s.
One if the most exciting areas of CAE is in logic synthesis
. The first elements of synthesis were seen in creating standard cell layout from schematics, describing the cells and their interconnection.
The benchmarks available under this project are Module Generation (Physical DA Workshop, 1989), Place and Route (Physical DA Workshop, 1987; MCNC Workshop, 1988), Logic Synthesis
(MCNC Workshop, 1987, 1989), Symbolic Layout and Compaction (MCNC Workshop, 1986), Test Generation, combined logic (ISCAS, 1985), Test Generation, sequential logic (ISCAS, 1989), and High Level Synthesis (SIDGA Workshop, 1989, currently under development).
Fuji Xerox employed the Genus Synthesis Solutions innovative early physical flow, which rapidly models physical effects such as placement and routing from the earliest stages of logic synthesis
. This capability helped them minimize gate area of SoC while also meeting performance targets, which led to improved power, performance and area (PPA) and faster time to market.
Methods of reversible logic synthesis
are quite different compared to traditional irreversible technologies [7-17].
Yang, Logic Synthesis
and Optimization Benchmarks User Guide: Version 3.0, Microelectronics Center of North Carolina (MCNC), 1991.
In , a 64-bit carry-select design case is presented, where the prediction logic synthesis
a priori assumes that single-cycle latency occurs when the carry propagation chain is shorter than 32 bits.