If one input is fixed to 1, the majority gate
functions like OR.
These designs have been implemented using three three-input majority gates in different ways with different propagation delay and consumed cells according to the form of majority gate's concatenation.
The main building block of QCA circuits is majority gate and consequently the other logic circuits are implemented based on majority gate networks.
Its functions are limited to three: (i) sending the preprocessed raw data to high-level processor, (ii) counting the number of the active majority gates (the active means that the output of a majority gate is 1), and (iii) generating the approximate sigmoid function for postprocessing based on artificial neural network.
The timing constraint on a QCA majority gate is that all three inputs are expected to reach the device cell (central cell) at the same time in order to have fair voting.
The fundamental QCA logic primitives are the three-input majority gate, wire, and inverter .
A scheme for modelling digital devices around five-input majority gate followed by a more feasible full adder unit has been framed with the target to achieve high device density in QCA designs.
The fundamental method for computing is majority gate or majority voter method  .
The majority gate produces an output that reflects the majority of the inputs.
Sulieman, "On the reliability of majority gates
full adders," IEEE Transactions on Nanotechnology, vol.