A log based arithmetic unit is employed on the mantissa
Since the hidden bit in mantissa
is always ' 1' as per IEEE 754 standard, there is no chance of getting 48th and 47th bit of the 24x24 bit multiplier as '0'.
In 32-bit IEEE-754 format, a number can be formed as follows: Bit 31 (MSB) is the sign bit, bits 30 through 23 represent the exponent, and bits 22 through 0 represent the fractional mantissa.
In addition to the combination of 16-bit and 32-bit data registers, the DSP's architecture has dedicated instructions that facilitate efficient implementation of floating-point mathematics: SIGNBITS returns the number of sign bits in a number, which can then be passed to ASHIFT, which shifts the radix point to normalize the mantissa.
A fixed-point number can be converted to floating point by determining the number of sign bits and normalizing the mantissa through shifting it by that number.
Shift the mantissa of the smaller number to the right by the difference between the exponents.
Unfortunately, in IEEE arithmetic [ANSI 1985] two singles hold fewer mantissa bits than a double, so we only get a 96-bit quad result.
We assume that our quad numbers are either in double-double format or in an IEEE style with 113 mantissa bits.
3), the decimal point follows the first mantissa word, not the first digit.
As shown in Section 5, our algorithm produces a 2N-bit mantissa with all but the last few bits correct.
More specifically, we assume that a double-precision number has 53 mantissa bits in memory and 64 in the registers.