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Its 7-stage pipeline alleviates cache memory cycle time bottleneck, while the system bus logic repartitioning reduces the amount of logic needing to run at the maximum CPU clock speed.
is the industry pioneer of high performance memory technologies such as multibanking, multibank caching, double data rate, fast cycle access, data streaming, terminated reduced-swing I/O switching, source-synchronous (wave-pipelining) data access, PLL-assisted clocking, ultra-fast charge sensing and ultra-fast memory cycle time.
The memory speed-to-price ratio is critical to graphics accelerator manufacturers; page mode memory cycle time is vital to the accelerator performance equation, yet total frame buffer memory (usually 1 or 2 Mbytes) often represents the bill of materials' most expensive item.
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