This increased performance is achieved by using state-of-the-art hardware for high-bandwidth communication between the FPGA and CPU modules, and by utilizing an efficient memory mapping scheme.
Section 5 presents a memory mapping scheme that can reduce the column-wise strided external memory access.
We address this problem by designing a custom memory mapping scheme (Section 5).
As for (2), it has been addressed by designing a semi-custom memory mapping controller which "tiles" the DRAM floor and "hops" between several tiles so as to minimize strided memory access.
The following set of optimizations are designed to eliminate virtual memory mapping changes and other per-page and per-fbuf costs associated with the baseline remapping mechanism.
When combined, the optimizations described eliminate all virtual memory mapping changes and other per-page and per-fbuf costs associated with cross-domain data transfer in the common case.
A virtual page remapping facility logically copies (or moves) a set of virtual memory pages among protection domains by modifying virtual memory mappings. The use of such a facility to create, destroy, and transfer a buffer aggregate involves the following steps.
Instead of working in the physical space defined by multi-dimension memory of a processor array, PDTs are developed within a memory mapping
In addition, the system supports shared "dynamic" memory mapping
, allowing drive developers to customize data and instruction memory allocation.
After a page fault, they usually return the appropriate page image to the kernel, which then establishes the virtual-to-physical memory mapping
(see Figure 1).
All virtual memory mapping
and address space manipulation in the application is handled by the operating system under the direction of ObjecStore, using normal system calls.
Recently it was found that both contents of memory mappings
and kernel memory could be leaked with Intel (INTC) x86 and Arm CPUs under a Meltdown attack.