pad limited

pad limited

A semiconductor chip that cannot be shrunk any further, because there would not be enough room for the bonding pads used for interconnection on the outer perimeter of the die. Although bonding pads are getting smaller, having shrunk below 50 microns, area array packaging has obviated the pad limited problem. See area array package.
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The comprehensive XC018 Master Kit for use with Cadence technology includes the Process Design Kit (PDK) as well as a low-power digital core library and I/O libraries for core and pad limited designs.
In order to provide optimum solutions for pad limited designs, the TC203 series is designed to use Toshiba high density, 62 um inner lead TAB bonding package technology.