per clock


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per clock

For each clock cycle. The phrase "the CPU does four instructions per clock" means that four machine instructions have been executed within one cycle of the CPU clock, the master clock that synchronizes everything in the computer. For example, in a 1 GHz computer, each clock cycle is 1 nanosecond long (one billion nanoseconds divided by one billion cycles). See clock.
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Its new architecture allows for wider dynamic execution -- meaning single instruction, multiple data per clock cycle.
This performance can be further improved to an equivalent of 150MHz clock rate by using the 25X "Dual-Output SPI" feature, which provides two bits of data per clock while maintaining the same 4-pin SPI interface.
The ST231 VLIW Core, which executes up to four operations per clock cycle, achieves performance comparable to a RISC processor running at a significantly higher clock frequency, while maintaining the low dynamic power consumption of its actual clock speed.
Intel(R) Wide Dynamic Execution -- Delivers more instructions per clock cycle, improving execution and energy efficiency.
It executes up to four operations per clock cycle, achieving performance comparable to a RISC processor running at a significantly higher clock frequency while maintaining the low dynamic power consumption of its actual clock speed.
E[acute accent]Future Geomagic software will take advantage of the Windows 64-bit architecture that provides greater memory support and the ability to process more data per clock cycle.
Operating at a clock rate of 1 GHz, each DSP is capable of executing up to 8 instructions per clock cycle for a peak processing performance of 8 GIPS per DSP or 72 GIPS for the entire board.
Mbytes; -- 112 double precision floating -- Total on board memory at point operations per clock 2 Gbytes; and per processor; and -- Reconfigurable logic -- 224 single precision floating capacity at 64 Mgates.
Just as we witnessed the move from CISC to RISC processors in the early 1990s, today we're seeing a new generation of systems that leverage industry-standard processors capable of supporting multiple floating-point operations per clock cycle, even as clock speeds continue to increase.
Affordable performance -- The C6412 DSP, an addition to the high- performance TMS320C6000(TM) roadmap, delivers 64 general-purpose 32-bit registers and its eight parallel functional units can compute four 16-bit multiply-accumulates (MACs) per clock cycle.
Targeted at networking applications, the 440GRx processor offers clock speeds up to 667 MHz, with a superscalar architecture that can execute two instructions per clock cycle.
This MIPS64-class processor can execute up to six instructions per clock cycle, into a pipeline that uses in-order issue, out-of-order and dispatch and execution and in-order retirement.