peripheral interconnect

peripheral interconnect

A pathway (channel, bus) between the CPU and peripheral devices. See peripheral bus.
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References in periodicals archive ?
Class 3 architecture requires redundant fabric switches for the backbone, redundant peripheral interconnect devices, and complete path redundancy (appropriate path failover software is required).
Conventional packaging methods using peripheral interconnects, such as quad flat packs (QFPs), small outline integrated circuits (SOICs), thin small outline packages (TSOPs), shrink small outline packages (SSOPs), and plastic leaded chip carriers (PLCCs), have reached their practical limit in production at somewhere over 200 pins.
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