The following designations are adopted on the diagram: CG: clock generator or source of clock frequency, DAC: digital-to-analog converter, Tr: trigger, DC: differentiating circuit, A: amplifier, FWR: full-wave rectifier, PDA: phase detector
of autocompensator, LPFA: the low-pass filter of the autocompensator, and the Sub: subtractor (located between the low pass filter of the PLL loop and the VCO).
The phase difference information of the phase detector
is firstly processed with an improved method and then sent to the controller to adjust the phase of the output clock.
In single phase systems two types of phase detectors
are used viz., the product type and Park transformation type.
(iii) Integrator plus lead/lag (voltage type phase detector
A fractional-N synthesizer system with analog correction was used in the design of a 10 kHz to 1 GHz signal generator to provide 10 Hz resolution based on a phase detector
rate of 40 kHz.
Figure 3 is the simulation result, the PLL is locked at the beginning, and phase of reference signal jumps at t = 500 s which leads to obvious jumping in the output of Phase Detector
. In Figure 3, the loop parameters of three PLLs are [[omega].sub.n] = 1,4, 10 and [xi] = [square root of 2]/2 and the amplitude of phase jumping is equal to 1/[10.sup.8] period of reference signal.
The main components of the phase detector
were two band-pass filters, two differential amplifiers, an analog-to-digital converter, a field programmable gate array chip, a digital signal processor chip, flash memory chips, and a liquid crystal display module.
Deployment of Phase Detectors
. When the two detectors are placed beside each other as in [6, 7, 21], the phase estimation error has a significant impact on the location estimation.
In a feedback loop, the oscillator is controlled by the output signal from the phase detector
Figure 2 shows a fairly general PLL arrangement with a phase detector
(PD), a low-pass loop filter [H.sub.L](s), a voltage controlled oscillator (VCO) in the forward path and a mixer, an intermediate frequency (IF) filter [H.sub.M](s), and a divider (/N).
KEY SPECS: The synthesizer achieves a phase detector
operating frequency of 110 MHz and simultaneously consumes less than 100 mW of power.
Designed to operate from external 6V DC (110V adapter provided) at up to 15,000 feet and 0 to 45 degC, the APPH6000RM-IS can be configured to meet user requirements: selectable internal or external reference source, phase detector
models, and frequency offset ranges.