phase jitter


Also found in: Dictionary, Thesaurus, Medical.

phase jitter

[′fāz ‚jid·ər]
(electronics)
Jitter that undesirably shortens or lengthens pulses intermittently during data processing or transmission.
References in periodicals archive ?
SiTime's SiT9121 and SiT9122 MEMS-based differential oscillators feature a high stability of up to [+ or -]10 ppm and 500 fs of integrated RMS phase jitter. They can serve in routers, servers, SATA / SAS / Fibre Channel HBAs, wireless base stations and 10G Ethernet switches.
The system supports 4x4 MIMO applications and several commercial standards including cellular, WiMAX, and WLAN and offers [+ or -]1-ns signal sampler synchronization, <1 ns peak-to-peak signal sampler jitter, and <1 degree of peak-to-peak RF-carrier phase jitter.
The LVE-PECL crystal oscillator RFX250 and LVE-PECL voltage-controlled crystal oscillator RFV250 feature phase jitter of < 0.5 ps and a frequency range from 600 MHz to 1.25 GHz.
Operating at 622.08 MHz over a temperature range of minus 40 to plus 85 degrees C, CTS Model 650 surface mount clock oscillators employ a patent-pending technology that provides typical RMS phase jitter of less than 1 pico-second, and excellent frequency stability of plus/minus 15 ppm.
With RMS phase jitter less than 500 fsec over the full 12 kHz-to-20 MHz integration range, the devices meet the jitter and phase noise requirements of applications such as 10G Ethernet, enterprise storage SAS and SATA, PCI Express Gen 1/2/3, PHY reference clocks and the newest generations of high-end FPGAs all while operating at about half the core power of competing devices.
[1]: Phase Jitter Modulation; an RFID technology that can quickly and accurately identify large volumes of tagged items stacked or stored in any physical orientation.
Features include low phase noise of -160 dB relative to the carrier per hertz (dBc/Hz), typical RMS phase jitter of 0.5 ps, and a low bit error rate.
It also accommodates 10-GHz clock and PLL applications and tests multiple differential data channels; isolation of jitter components such as RJ and DJ to get total jitter at [10.sup.-6] and [10.sup.-12]; jitter accumulation; skew; period accuracy; phase jitter to [10.sup.-6] and [10.sup.-12]; and FFT of power spectral density.
With phase jitter at < 0.5 ps and frequencies from 600 MHz to 1.25 GHz, the series is ideal for applications such as SONET, SDH, ATM and WAN.
With RMS phase jitter less than 500 fsec over the full 12 kHz to 20 MHz integration range, the new devices meet the stringent jitter and phase noise requirements of applications and standards such as 10G Ethernet, enterprise storage SAS and SATA, PCI Express Gen 1/2/3, XAUI, SRIO, stringent PHY reference clocks and the newest generations of high-end FPGAs all while operating at about half the core power of competing devices.
Due to its MEMS technology design, phase jitter is low being typically 0.7 ps at 200 MHz.
Given a signal with L(fm) single sideband phase noise characteristics, the phase jitter (in radians) is given by