phase-locked loop

[′fāz ¦läkt ′lüp]

(electronics)

A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL.

PLL

(Phase-Locked Loop) An electronic circuit that compares an input frequency and phase to a reference signal. It then generates a voltage proportional to the difference between the input and the reference. PLLs are used in myriad digital and mixed mode (analog and digital) applications as regulators, demodulators, synchronizers and frequency multipliers and dividers. For example, in a superheterodyne FM radio, a PLL is used to lock the local oscillator to an accurate frequency reference such as a crystal or ceramic resonator. It can also be used to demodulate the FM audio and stereo subcarrier signals from the intermediate frequency (IF) stage. See heterodyning.

PLLs in an FM Radio

This example shows how PLLs are used for regulation and demodulation in an FM radio tuned to 101.5 MHz. The FM frequency range is 88-108 MHz, and this example uses a 10.7 MHz intermediate frequency (IF) and a 1 MHz reference frequency.

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References in periodicals archive ?

A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking, IEEE Journal of Solid-State Circuits 46(8): 1870-1880.

Analysis of frequency synthesisers for multistandart wireless transceiver/Daznio sintezatoriu daugiastandarciams bevielio rysio siustuvams IR imtuvams analize

The Modeling for All-Digital Phase-Locked Loop. Figure 1(a) shows the phase domain model of a second-order analogy PLL.

FPGA-based implementation of all-digital QPSK carrier recovery loop combining costas loop and maximum likelihood frequency estimator

The important part of the phase-locked loop (PLL) is phase detector.

Optimization of Fractional-N-PLL frequency synthesizer for power effective design

"At the other end of the frequency spectrum, this same 3.3 Volt VCXO easily handles phase-locked loop applications right up to 125 MHz."

SARONIX OFFERS ST1307/ST1317 HIGH-FREQUENCY VCXO'S

In some cases, the use of crystal filters or phase-locked loops can be used to reduce the noise.

A Sampling of RF Synthesizers

In this way, the phase of the bit synchronized clock can be changed and adjusted constantly in the phase-locked loop until the accurate synchronization signal is obtained [3].

Improved Design of Bit Synchronization Clock Extraction in Digital Communication System

In light of major ongoing restructuring in the power system and the proliferation of new devices, Karimi-Ghartemani summarizes his experience from working with different phase-locked loop structures for power and energy applications.

Enhanced Phase-Locked Loop Structures for Power and Energy Applications

TSMC's 28nm reference phase-locked loop (PLL) design was used to validate Synopsys' comprehensive custom solution while demonstrating productivity-enhancing capabilities of the TSMC AMS Reference Flow 1.0.

Synopsys' solution to be validated in collaboration with TSMC

The reference signal generated by a phase-locked loop (PLL) affects the performance of custom power devices for compensating power factor, harmonic current, and voltage disturbances.

Novel phase-locked loop using adaptive notch filter/Adaptyvaus uztvarinio filtro taikymas fazineje kilpoje