phase-locked loop


Also found in: Acronyms, Wikipedia.

phase-locked loop

[′fāz ¦läkt ′lüp]
(electronics)
A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL.
References in periodicals archive ?
The company's first product, PLL Noise Analyzer, the industry's first noise analysis tool for phase-locked loops (PLLs), has already been adopted by semiconductor industry leaders.
Faraday's analog and mixed-signal design teams are using Sandwork's tools to debug high-speed, high-precision, high-accuracy designs such as analog-digital converters (ADCs), phase-locked loops (PLLs), and network semiconductor intellectual property (SIP).
VIA's design teams are using Sandwork's tools to debug DVD decoder designs and PC-related project designs containing analog-digital converters (ADCs), phase-locked loops (PLLs), and other analog and mixed-signal devices.
The device integrates such components as three independent phase-locked loops (PLLs) with non-integer frequency multiplication capabilities, spread-spectrum generation, independent post dividers, and universal output buffers.
The company also announced its initial product, PLL Noise Analyzer(TM), the industry's first noise analysis tool for circuits containing phase-locked loops (PLLs) (see today's related press release).
a new analog/RF electronic design automation company, today announced its initial product, PLL Noise Analyzer(TM), the industry's first noise analysis tool for high-performance analog/RF integrated circuits containing phase-locked loops (PLLs).

Full browser ?