primary cache

primary cache

[¦prī‚mer·ē ′kash]
(computer science)
A cache memory located within a microprocessor chip itself. Also known as internal cache; level 1 cache.

primary cache

(hardware, architecture)
(L1 cache, level one cache) A small, fast cache memory inside or close to the CPU chip.

For example, an Intel 80486 has an eight-kilobyte on-chip cache, and most Pentiums have a 16-KB on-chip level one cache that consists of an 8-KB instruction cache and an 8-KB data cache.

The larger, slower secondary cache is normally connected to the CPU via its external bus.
References in periodicals archive ?
Each chipset hosts up to 8 cores, equipped with a 256 KB primary cache, as well as a secondary cache of up to 24 MB, an I/O processor, a memory controller, and a system controller.
The system leaves a copy of frequently accessed data in primary cache for very fast retrieval.
Primary controller transfers the data into the primary cache
They find the average memory access time to the primary cache alone to go up from 1.
In addition, the SH-MobileR2's 64Kbyte primary cache memory (32Kbytes each for instructions and data) is supplemented by a new 256Kbyte secondary cache memory (mixed instructions and data) that contributes to faster software execution.
An on-chip 64 KB primary cache (32 KB instruction, 32 KB data) offers faster access to frequently used operations and data.
Internet content is being multicast from a primary cache at the warehouse through Teleglobe's Des Laurentides earth station to multiple ISP kiosk sites around the world over the INTELSAT 603 satellite at 335.
The Internet content will be multicast from a primary cache at the warehouse through one of Teleglobe's INTELSAT earth stations to kiosk sites in the UK, the US, Brazil, France, Cyprus, Egypt, the Netherlands, Canada and Sweden.
L2 cache, or secondary cache, is high speed memory placed between the Level One (L1), or primary cache, and the main memory, which is most often composed of DRAM components.
Key Features of TX49 Core -- Optimized 5-stage pipeline -- Upward-compatible Instruction Set -- MIPS I, II and III Instruction Set Architecture (ISA) -- Multiply and Add Instruction -- Pre-fetch Instruction -- Built-in, high-capacity primary cache memory -- Instruction cache 8k/16k/32kbyte (selectable) 4 way set associative/Lock function -- Data cache 8k/16k/32kbyte (selectable) 4-way set associative/Lock function -- Single or double-precision floating-point unit (option) -- 48 built-in double-entry joint-Translation Look-aside Buffers(TLB) -- Low power consumption modes/halt and doze modes -- Power supply: 3.
To speed data flow, the processor supports large register files and features a large on-chip primary cache with 32 kilobytes for instructions and 32 kilobytes for data.