register allocation

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register allocation

(compiler, algorithm)
The phase of a compiler that determines which values will be placed in registers. Register allocation may be combined with register assignment.

This problem can be shown to be isomorphic to graph colouring by relating values to nodes in the graph and registers to colours. Values (nodes) which must be valid simultaneously are linked by edges and cannot be stored in the same register (coloured the same).

See also register dancing and register spilling.

[Preston Briggs, PhD thesis, Rice University, April 1992 "Register Allocation via Graph Coloring"].
This article is provided by FOLDOC - Free Online Dictionary of Computing (
References in periodicals archive ?
Since new variables are possibly introduced at different stages, linear register allocation is performed on each BB, for each processor core.
During compilation, the decision of which variables to be kept in registers at each point in the generated code is called register allocation. Typically, register allocation is modeled as a graph coloring program which is aimed at finding a k-optimal-coloring solution for the interference graph.
Under this level, ORC only goes through the basic phases when compiling source code, such as code selection, local schedule, local register allocation, and code emission, and has no optimization.
The main contributions of this work are (1) force-balanced-two-phase (FBTP) instruction scheduling algorithm to minimize unnecessary inter-cluster data communications and balance the distribution of the access to global register file among the whole execution time; (2) localization-enhanced (LE) register allocation mechanism to minimize unnecessary global register allocation.
The largely Asian researchers propose software watermarking by register allocation, a financial crisis prediction model based on XBRL, a PAPR reduction technique for OFDM-WLAN, and meta-heuristic MAS optimization for supply chain procurement.
This can lead to sub-optimal register allocation and pointer assignments, redundant code and inconsistent variable declarations.
Andrew Cambridge University Press 2002 ISBN 0-521-82060- This textbook describes all phases of a compiler: lexical analysis, parsing, abstract syntax, semantic actions, intermediate representations, instruction selection via tree matching, dataflow analysis, graph-coloring register allocation, and runtime systems.
The task of register allocation is to map virtual registers (e.g., variables, temporaries, constants) to a limited number of physical registers.
Additionally, this representation is used by the compiler to perform target-specific transformations, including register allocation, instruction scheduling, and branch prediction.
It is observed in [5-6] that this phase coupling is especially important in relation of instruction selection, register allocation, and instruction scheduling phases, due to non-orthogonal instruction set with instruction level parallelism.
Some specific subjects investigated are packet reordering analysis for LEO satellite networks, address register allocation in digital signal processors, data aggregation with multiple spanning trees in wireless sensor networks, and design of fuzzy feed-forward decoupling systems based on FPGA.