"A SISO Register Circuit
Tailored for Input Data with Low Transition Probability", Computers IEEE Transactions on, 66: 45 -51.
The main components are a sample-and-hold (S/H) circuit, pont divisor circuit, series of comparators circuits, a multiplexer based encoder circuit, and DFF register circuit
. A sample and hold (S/H) circuit is employed to sample and amplify the pixel signal.
In this design, the PISO register circuit
was configured from D-FF with load and clock control, as Figure 8 indicates.
The quantum shift register circuit
is represented by a set of input qubits, memory qubits, a set of output qubits, and updated memory qubits.
6.2: Serial in parallel out shift register circuit.
6.3: Parallel in serial out shift register circuit.