reset condition

reset condition

[′rē‚set kən‚dish·ən]
(electronics)
Condition of a flip-flop circuit in which the internal state of the flip-flop is reset to zero.
References in periodicals archive ?
For this thicker [Al.sub.2][O.sub.3], the limit in [CC.sub.SET] is set to 100 [micro]A, whereas [CC.sub.RESET] = 100 mA; both are large current densities flowing through the oxide layer and that would increase the chances for leaving large amount of residuals (after the RESET condition which produce localized Joule heating in the previously formed conductive filament) in the form of a high density of oxygen vacancies (neutral or charged) and/or metal ions.
Unfortunately, the NCO was free running after the chip was released from the reset condition. Its phase could not be separately controlled.
These elements can be used to compensate the offset by toggling the Set/Reset elements between set and reset conditions (***, 2002; Caruso, 2003).