sample-and-hold circuit

sample-and-hold circuit

[¦sam·pəl ən ′hōld ‚sər·kət]
(electronics)
A circuit that measures an input signal at a series of definite times, and whose output remains constant at a value corresponding to the most recent measurement until the next measurement is made.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.
References in periodicals archive ?
The signal processing circuit was composed of a bias circuit, a spinning current circuit, a clock logic-controlled circuit, an oscillator, an amplifier, a sample-and-hold circuit, a comparator, and an output-stage circuit.
The excitation signal (channel 2) and sampling signal for the sample-and-hold circuit (channel 1) are shown in Figure 9.
Although an SAR ADC usually requires a sample-and-hold circuit on its input, the Microchip dsPIC devices do not.
Next, one may compare this to the output of a sample-and-hold circuit that has a low impedance load, as shown in Figure 5.
The resulting poor hold duration manifests itself as an increasing inability of the sample-and-hold circuit to isolate the periodic sampling function discrete-line spectra from the output of the sample-and-hold circuit.
The first two of a family of signal-conditioning expansion boards, part numbers MSXB 064 and MSXB 065, provide differential instrumentation amplifiers with optional sample-and-hold circuits and jumper-selectable gains of 1, 5 and 25.
Low-power consumption (<5 =B5W) extends battery life, low leakage currents (100 pA max) lengthen hold times in sample-and-hold circuits and fast switching speeds (tON =3D 150 ns max, tOFF =3D 100 ns max) reduce propagation delay in timing sensitive applications.