scan register

scan register

(circuit design) A digital logic circuit which can act either as a flip-flop or as a serial shift register and which is used to form a scan path.

The most common design is a multiplexed flip-flop:

___ ____ normal in --| \ | | | |------|D Q|---- normal/scan output scan in ----|___/ mux | | | | | test mode ----+ +----|> | flip-flop | |____| clk ---------------+

The addition of a multiplexor (mux) to each flip-flop's input allows operation in either normal or test mode. The output of each flip-flop goes to the normal functional logic as well as to the scan input of the next multiplexor in the scan path.

The other common design is level-sensitive scan design (LSSD).
This article is provided by FOLDOC - Free Online Dictionary of Computing (
References in periodicals archive ?
A BSDL file provided by the ICT is the only link between the test development engineer and the silicon device that describes the correct boundary scan cell type, sequence and number of cells, manufacturing identity code, boundary scan register length and other related information (FIGURE 1).
Sometimes, embedded instruments such as BIST and microprocessor emulation/debug registers also are included although often we find that the absence of a boundary scan register unnecessarily makes board-level testing more complex and expensive than necessary.
The eventual solution centered on the concept of embedding an internal shift register around the perimeter of semiconductor devices, a boundary scan register.
The resulting BSDL file describes the boundary-scan characteristics of the device including scan register length, ID code (if present), instruction codes, and I/O lists.
This section evaluates linear scan register allocation in terms of both compile-time performance and the quality of the resulting code.
To detect and isolate the above defects, the tester is shifting the patterns shown in Figure 1 into the Ul boundary scan register and applying these pat terns to the inputs of U2.
Given the large cone of logic behind each scan register, any change in state on the register's output can cause a large number of dependent gates to switch states, causing current to spike.
Example UUT BSR = Boundary Scan Register Host Bus Data Data Minimum Effective Packet Frame to be Transmission Bandwidth Size Size Transmitted Time PXI 500 Mb/s 1 B 4 B 1.6 GB 105 s PXI Express x 1 2 Gb/s 4,096 B 4,124 B 1.6 GB 7 s Table 2.
Although programming can be accomplished with this sort of layout, changing the values of the flash device's write enable (WE) pin through the boundary scan register would be very time-consuming.
The Interconnect Test is used to detect faults on nets that can be directly controlled and observed by boundary scan register cells.
A 1500-compliant device also does not mandate 1149.1, but the core wrappers are based on the concept of a boundary scan register. Top-level control of the wrapper functions can be done through the 1149.1 TAP if it exists on the device.
To provide access to these test points, all boundary scan cells of a device are linked together to the boundary scan register, which is accessible from the outside through the test access port (TAP).