The four-way set-associative cache
memory is divided into two 32 Kbyte areas, one for instructions and one for data.
To further understand the nature of capacity/conflict misses, we determined the minimum cache size necessary to remove each capacity miss that occurs in an 32KB two-way set-associative cache with a 32-byte block (Figure 18), and the minimum associativity required to remove each conflict miss that occurs in the same cache for intranest, internest, and whole-program misses (Figure 19).
A four-way set-associative cache removes 36% of intranest conflict misses.
A direct-mapped cache is commonly used in microprocessors with a very high clock speed, since its lookup process is faster than that of a set-associative cache
The SH7397's high-performance SH-4A CPU core has two separate 32-Kbyte, 4-way set-associative cache
memories -- one for instructions and the other for data -- to improve the cache hit rate for higher throughput.
The cache considered is an 8KB two-way set-associative cache
with 128 cache sets and four data elements per cache line.
The on-chip 16-KB 4-way set-associative cache
helps improve the cache hit-rate in program execution.
Based on the ARM720T core, the CS89712 features an integrated 64-entry MMU, 8 kbytes of four-way, set-associative cache
, and on-chip 10-Mbps Ethernet MAC and PHY interfaces.
The 5Kc features a six-stage pipeline with branch control and single-cycle execution for most instructions, a co-processor interface, a 64-entry MMU, and up to 64 kbytes each of 4-way set-associative cache
Opal features a six-stage pipeline with branch control and single-cycle execution for most instructions, a co-processor interface for FPUs, a 64-entry MMU, and up to 64 kbytes each of 4-way set-associative cache
In addition to the single-cycle MAC, many of the MIPS32 4Km features, such as the 32-bit arithmetic unit, large register file (32 general-purpose 32-bit registers) and 4-way set-associative cache
controller, are optimized for embedded systems.
The two-way set-associative caches
are nonblocking and support cache line locking.