set-associative cache

set-associative cache

[′set ə‚sȯs·ē‚ād·iv ‚kash]
(computer science)
A cache memory in which incoming data are distributed in sequence to each of two to eight areas or sets, and is generally read out in the same manner, allowing each set to prepare for the next input/output operation.
References in periodicals archive ?
The four-way set-associative cache memory is divided into two 32 Kbyte areas, one for instructions and one for data.
The SH7397's high-performance SH-4A CPU core has two separate 32-Kbyte, 4-way set-associative cache memories -- one for instructions and the other for data -- to improve the cache hit rate for higher throughput.
Incorporates a large four-way set-associative cache memory (32K-byte instruction cache and 32K-byte data cache) that realizes an increased hit ratio and supports higher performance than the previous generation product.
Based on the ARM720T core, the CS89712 features an integrated 64-entry MMU, 8 kbytes of four-way, set-associative cache, and on-chip 10-Mbps Ethernet MAC and PHY interfaces.
The 5Kc features a six-stage pipeline with branch control and single-cycle execution for most instructions, a co-processor interface, a 64-entry MMU, and up to 64 kbytes each of 4-way set-associative cache.
The 5Kc core features a six-stage pipeline with branch control and single-cycle execution for most instructions, a co-processor interface, a 64-entry MMU, and up to 64 kbytes each of 4-way set-associative cache.
Opal features a six-stage pipeline with branch control and single-cycle execution for most instructions, a co-processor interface for FPUs, a 64-entry MMU, and up to 64 kbytes each of 4-way set-associative cache.
In addition to the single-cycle MAC, many of the MIPS32 4Km features, such as the 32-bit arithmetic unit, large register file (32 general-purpose 32-bit registers) and 4-way set-associative cache controller, are optimized for embedded systems.
A MODE input pin permits use of the P4C214 as a Direct-Mapped cache (all 14 address bits latched) or a 2-way Set-Associative cache (only high order 13 address bits latched).
Because of a two-way set-associative cache design, RISC System/6000 processors are very efficient and able to achieve comparable or better performance results than other systems that have larger caches.
The two-way set-associative caches are nonblocking and support cache line locking.