The four-way set-associative cache
memory is divided into two 32 Kbyte areas, one for instructions and one for data.
To further understand the nature of capacity/conflict misses, we determined the minimum cache size necessary to remove each capacity miss that occurs in an 32KB two-way set-associative cache with a 32-byte block (Figure 18), and the minimum associativity required to remove each conflict miss that occurs in the same cache for intranest, internest, and whole-program misses (Figure 19).
A four-way set-associative cache removes 36% of intranest conflict misses.
In this section, We compare similarities and differences on Alpha traces between SPEC'95 on a 32KB, 32-byte block, two-way set-associative cache and the Perfect Benchmarks on an 8KB, 32-byte block, direct-mapped cache.
A direct-mapped cache is commonly used in microprocessors with a very high clock speed, since its lookup process is faster than that of a set-associative cache [Hill 1988].
Their experiments show that a CML buffer enables a large direct-mapped cache to perform nearly as well as a two-way set-associative cache of equivalent size and speed.
Section 4.4 discusses the application of TPCM to set-associative caches. Section 4.5 shows that a TRG yields a stronger linear relationship between conflict-metric values and cache miss rates than does a WCG.
The cache considered is an 8KB two-way set-associative cache with 128 cache sets and four data elements per cache line.
For a k-way set-associative cache, a miss occurs if, between consecutive accesses to a particular memory line, at least k other accesses occur to distinct memory lines that map to the same cache set.
In a k-way set-associative cache k distinct contentions are needed before a replacement miss will occur at i along the reuse vector r.
Such caches are called W-way set-associative caches
. With such cache architecture, memory addresses are used to index these caches.
The two-way set-associative caches
are nonblocking and support cache line locking.