structured ASIC


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structured ASIC

A type of application specific IC (ASIC) chip that contains blocks of logic, called "tiles" or "modules," that have their transistors already wired together forming gates along with some combination of multiplexors, flip/flops, look up tables and the like. Some vendors also include blocks of RAM. Unlike a standard cell, which requires all the masking stages in the transistors and metallization layers to be fabricated, structured ASICs require only one or two masks to tie the tiles together. In one design, only the vias need to be made conductive in order to complete the chip. See ASIC and via.
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eASIC is a fabless semiconductor company offering breakthrough Structured ASIC devices aimed at dramatically reducing the overall fabrication cost and time of customized semiconductor chips.
Altera's Quartus II design software is a technologically advanced development software for FPGA, CPLD, and structured ASIC designs.
(Nasdaq:LAVA), a provider of semiconductor design software, has announced that STMicroelectronics (NYSE:STM) has successfully implemented a via-programmable embedded structured ASIC platform using Magma's Blast Create(TM) SA.
Engineers can simplify the job of SOC design and avoid purchasing and learning some of the SOC EDA toolkit (tools for circuit, mask, and physical designers) by using a structured ASIC design flow.
The expanded EasyPath product line now supports the Xilinx Spartan-3 and Virtex-4 Platform FPGAs, starting at just $12.95 for 30,000 logic cells and half the price of comparable Structured ASIC offerings.
The resulting Mainstream IV8102 device--said to be the world's first ASIC capable of processing 4SIF/DI (704 X 480 pixels) resolution MPEG4 video at 30 frames per second entirely on-chip--was created using intellectual property developed in-house at IndigoVision, and implemented on a 0.25[micro] Structured ASIC from ChipX.
Structured ASIC technologies such as NEC Electronics' Instant Silicon Solution Platform[TM] (ISSP[TM]) feature lower NRE costs and a shorter design and fabrication cycle than a cell-based device through preconfiguration of some of the logic, memory and I/O embedded in the device.

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