structured ASIC


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structured ASIC

A type of application specific IC (ASIC) chip that contains blocks of logic, called "tiles" or "modules," that have their transistors already wired together forming gates along with some combination of multiplexors, flip/flops, look up tables and the like. Some vendors also include blocks of RAM. Unlike a standard cell, which requires all the masking stages in the transistors and metallization layers to be fabricated, structured ASICs require only one or two masks to tie the tiles together. In one design, only the vias need to be made conductive in order to complete the chip. See ASIC and via.
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eASIC is a fabless semiconductor company offering breakthrough Structured ASIC devices aimed at dramatically reducing the overall fabrication cost and time of customized semiconductor chips.
Blast Create SA's structure-specific timing optimization allowed us to manage the mapping of the RTL into the programmable logic cells, enabling us to fully leverage the structured ASIC fabric embedded in our Spear(TM) product, achieve timing and minimize area.
Not surprisingly, IndigoVision evaluated several Structured ASIC vendors before settling on ChipX.
This brings additional off-the-shelf alternatives to those designers contemplating a Structured ASIC solution.
For low- and mid-volume applications that require as few as 500 units to as many as 100,000 units and demand an ASIC-type performance, a structured ASIC offers a desirable alternative.
Keep in mind the fact that many of the new Structured ASIC technologies have complex pin assignment rules.

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