Adders/subtractors 1343 12-bit adder 255 13-bit adder 136 14-bit adder 68 15-bit adder 34 16-bit adder 17 4-bit subtractor
17 8-bit adder 816 Comparators 2 6-bit comparator equal 1 6-bit comparator greater 1 Counters 21 4-bit up counter 17 5-bit up counter 2 6-bit up counter 2 Registers 76 16-bit register 16 8-bit register 60 12-bit latches 272 Table 4: Comparison among VLSI implementations of VBSME architectures.
To realize the three reversible fused elements, the proposed design requires a reversible single precision floating point adder, a reversible single precision floating point subtractor and a reversible single precision floating point multiplier.
In the above figure, Reversible fused add-subtract (RFFAS) represents the realization of a reversible single precision floating point adder and subtractor as a single unit.
The number of arithmetic elements, such as adders and subtractors for generating weighting coefficients, are less than the bi-cubic  and winscale  image interpolations.
The number of arithmetic elements like adders and subtractors used for generating weighting coefficients are very less than the bi-cubic algorithm.
Typically, two subtractors with a multiplexer are employed to calculate the absolute value of the difference (v -[v.ref]) as shown in Figure 12.
For 8-bit architectures, no power reduction is achieved by operand isolation, because the additional power consumed in the de-multiplexer and the encoding logic (due to logic hazards) compensates the power savings obtained by the subtractors. However, wider architectures with operand isolation achieves power savings of 10%, equivalent to 20% with respect to Loop-arch, at processing latencies below 10 ns.
(i) designing an architecture for adder and subtractor by the minimal figure of cells, utilization area, and overall depleted energy,
Section 3 spotlights existing works on adder and subtractor. In Section 4, the proposed designs are formed in terms of cells fabrication and input and output positions.
It consists of a multiplier that computes the auxiliary input sequence, a permutation block that permute the input sequence in an appropriate order and two MUXs and a adder/ subtractor
used to obtain the input sequences in the necessary form as shown in equation (10).
In order to obtain cosine data from the new pipeline process, we put forward unidirectional rotation method to reduce the comparator and choose addition or subtractor
. [[theta].sub.m+1] should be expressed firstly.
Model 1 is the filter without retiming and with adder, subtractor
, multiplier, and delay elements.