transmission gate

transmission gate

[tranz′mish·ən ‚gāt]
(electronics)
A gate circuit that delivers an output waveform that is a replica of a selected input during a specific time interval which is determined by a control signal.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.
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The aspect for improving the performance of circuits based on CMOS logic resulted in introduction of many logic styles like Pass Transistor logic (PTL), Transmission Gate logic (TG), Double Pass Transistor logic (DPTL) and also many other hybrid logics.
In our design the transmission gate is used instead of NAND gate to produce a monocycle pulse of UWB with comparable low power, good balance between the positive and negative parts, and relatively small ringing level.
The CMOS transmission gate consists of two MOSFETs, one n-channel responsible for correct transmission of logic zeros, and one p-channel, responsible for correct transmission of logic ones [11].
Since an inverter followed by transmission gate is equivalent to a clocked inverter, the combination is replaced by a clocked inverter to form a [C.sup.2]MOS based flip-flop architecture as shown in Figure 3 [23].
The first device is a solid-state transmission gate (t-gate) multiplexer that uses CNT as a channel in the Field Effect Transistors (FET) of both n-FET and p-FET types that are used.
Resulting, using transmission gate in EBC and TG enjoys the least power, delay, and PDP as a complete part that does not need any mechanisms.
The next design is Transmission Gate Adder (TGA) [11].
One uses two high-[V.sub.th] NMOS pass transistors for accessing the data retention cell (DRC), the other uses a pass transistor and a transmission gate for accessing the DRC.
A CMOS implementation for the recursive circuit shown in Fig 4..For multiplexers and AND gates using the TSMC library executions while for the XOR gate we have used the faster ten transistor implementation based on transmission gate XOR to tie the delay with AND gates.
On the rising edge of the clock, the transmission gate ([T.sub.2]) of the slave stage is turned on, so that the value of node A, which is sampled right before the rising edge, propagates to the output Q.
"Combinational Circuits Using Transmission Gate Logic for Power Optimization." International Research Journal of Engineering and Technology, 3.5: 649-654 ISSN: 2395-0056

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