It can be seen that the voltages are balanced, as shown in the

voltage phasor diagram.

UPFC is able to provide simultaneous real-time control of the

voltage phasor at a distinguished bus and the impedance of a branch, in which UPFC operates, determining the active and reactive power flowing through the mentioned branch.

Previous research about PMU placement have assumed that a PMU could be located at a bus and provide bus

voltage phasor, as well as current phasor along all branches incident to the bus.

If the torque error between +ve and -ve torque windows, then the

voltage phasor could be at zero state.

In which [I'.sub.a] is the value of phase and [V.sub.fa] is

voltage phasor. However, since the location of the fault, i.e.

The vital rule of PMU placement is that, when a PMU is placed on a bus, it can measure the

voltage phasor on that bus, as well as on the buses on the other end of all the connected lines, using the measured current phasor and the known transmission line impedance [9].

As shown in Figure 2(a), N represents linear time invariant circuit,

voltage phasor of its independent excitation voltage is [[??].sub.s],

voltage phasor of output is [[??].sub.0], and x is a passive component.

where [E.sup.*.sub.k]: complex conjugated

voltage phasor at bus k, [P.sup.sp.sub.k], [Q.sup.sp.sub.k]: specified active and reactive net powers at bus k, [Y.sub.ki] = [G.sub.ki] + [jB.sub.ki]: bus admittance matrix element, and [E.sub.i]:

voltage phasor at bus i.

From the definition (43a), and since all expansion elements of [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII], and [[[[??].sup.E.sub.i[xi]](t)].sub.v'] are equal to zero, the [v.sub.o] x [v.sub.o] TRCM matrix [MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] relating the vectorial

voltage phasor of the incident path with the resultant of all consequent reflected ones on the TL of incidence infinitesimally before the discontinuity as

Gopakumar, "Asymmetric multilevel converter for high resolution

voltage phasor generation", in Proc.

This is achieved by injecting an appropriate

Voltage phasor in series with the line; this

Voltage phasor can be viewed as the Voltage across impedance in series with the line.

where [V.sub.AC] is the AC

voltage phasor, [V.sub.DC-Link] is the voltage at the common DC bus, and [P.sub.mr] and [P.sub.mi] are the pulse modulation factors on the real and imaginary axes.