wait state

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wait state

[′wāt ‚stāt]
(computer science)
The state of a computer program in which it cannot use the central processing unit normally because the unit is waiting to complete an input/output operation.

wait state

(architecture)
A delay of one or more clock cycles added to a processor's instruction execution time to allow it to communicate with slow external devices. The number and duration of wait states may be pre-configured or they may be controlled dynamically via certain control lines.

wait state

The time spent waiting for an operation to take place. Wait states are often idle computer cycles, because a computer's CPU is much faster than main memory. Wait states are introduced between the time the CPU requests data from the RAM (an address is placed on the address bus) until the content has been delivered to the CPU. See address bus.
References in periodicals archive ?
GSI Technology (Nasdaq:GSIT) today announced the availability of its 144Mb NBT[TM] (No Bus Turnaround) SRAM that supports back-to-back Read/Write operation with no wait states.
The new RSC-4x Demo/Evaluation Toolkit V2 includes an RSC-4x-based evaluation board with upgrades such as a USB interface, 0 wait states for improved quality synthesis, and 32MBytes of serial flash memory for storing synthesized speech.
The 6x5 Smart Speed crossbar switch nearly eliminates wait states.
In addition, Liberating Tech takes advantage of the 25 nanosecond performance of the nvSRAM to eliminate wait states for the processor, making it highly efficient.
This eliminates the need seen with other instruments to slow down tests by adding wait states to ensure the signal generator has settled.
MX31 multimedia applications processors virtually eliminates wait states and enables the processor to attain equivalent performance to processors with clock speeds up to 3.
System parallelism is accomplished via the 6x5 Smart Speed crossbar switch that nearly eliminates wait states and enables the processor to drive equivalent performance to processors with clock speeds up to 3 GHz, but without the power consumption penalty that goes with higher operating frequencies.
To diagnose user related problems, administrators need a clear understanding of the SQL workload, its associated wait states and key performance metrics.
Users can expect to achieve 132 MB/sec PCI bus performance with zero wait states while easily meeting stringent power requirements of portable PCI applications like mini PCI modules or CardBus cards.
An integrated 32-byte bi-directional FIFO buffer memory supports zero wait state burst operation or programmable wait states from zero through seven.